Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT) is a robust alternative to classical structural ATPG. Due to the powerful reasoning engines of modern SAT solvers, SAT-based algorithms typically provide a high test coverage because of the ability to reliably classify hard-to-detect faults. However, a drawback of SAT-based ATPG is the test compaction ability. In this paper, we propose an enhanced dynamic test compaction approach which leverages the high implicative power of modern SAT solvers. Fault detection constraints are encoded into the SAT instance and a formal optimization procedure is applied to increase the detection ability of the generated tests. Experiments show that the proposed approach is able to achieve high compaction -- for certain benchmarks even smaller test sets than the currently best known results are obtained.

http://www.informatik.uni-bremen.de/agra/doc/konf/13ICCAD-SAT-FDC.pdf

Improved SAT-based ATPG: more constraints, better compaction

Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.

/pdf/tiguan-thread-parallel-integrated-test-pattern-generator-4fn410bkzb.pdf

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis

Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g., due to environmental radiation. Approaches to implement fault tolerance are known. But assessing the fault tolerance of a given implementation is a hard verification problem. Here, we propose the use of formal methods to assess the robustness of a digital circuit with respect to transient faults. Our formal model uses a fixed bound in time and exploits fault detection circuitry to cope with the complexity of the underlying sequential equivalence check. As a result, a lower and an upper bound on the robustness are returned together with vulnerable components. The underlying algorithm and techniques to improve the efficiency are presented. In experiments, we evaluate the method on circuits with different fault detection mechanisms.

Effective Robustness Analysis Using Bounded Model Checking Techniques

Decision procedures are used as core technique in many applications today. In this context, automated reasoning based on Satisfiability Modulo Theories (SMT) is very effective. However, developers have to decide which concrete engine to use and how to integrate the engine into the application. Even if file formats like SMTLIB standardize the input of many engines, advanced features remain unused and the integration of the engine is left to the programmer. This work presents metaSMT, a framework that integrates advanced reasoning engines into the program code of the respective application. metaSMT provides an easy to use language that allows engine independent programming while gaining from high performance reasoning engines. State-of-the-art solvers for satisfiability and other theories are available for the user via metaSMT with minimal programming effort. For two examples we show how metaSMT is used in current research projects.

metaSMT: Focus on Your Application not on Solver Integration.

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the solving process. In this paper, we present a technique that applies structural knowledge about the circuit during the transformation. As a result, the size of the problem instances decreases, as well as the run time of the ATPG process. The technique was implemented, and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. It is shown that the overall performance of an industrial framework can significantly be improved. Further experiments show the benefits with regard to the efficiency and robustness of the combined approach.

Short Papers On Acceleration of SAT-Based ATPG for Industrial Designs

In an arrangement for testing an integrated circuit comprising a combinational logic system, which arrangement performs a test of the behavior of the combinational logic system in comparison with test software which emulates the nominal behavior of the integrated circuit, the signal edge behavior of the combination logic system is checked in that that the test software comprises two identical software models of the combinational logic system to be tested, in which a test sample is applied for test purposes to a first of these software models and whose output signals are coupled to a second of these software models, in that the integrated circuit comprises a test circuit which, in a test mode, applies a first test sample in a first test clock cycle to the input of the combinational logic system of the integrated circuit and takes over the output signal in a buffer memory and which feeds back this output signal as a second test sample in a second test clock cycle to the input of the combinational logic system and again takes over the output signal of the combinational logic system in the buffer memory, and in that at the end of the second test clock cycle, the arrangement compares the results of the combinational logic system of the integrated circuit in the buffer memory with the results of the second software model.

Arrangement and method of testing an integrated circuit

An integrated circuit comprises a BIST architecture having a linear feedback shift register, a BIST controller for controlling a seed value supplied to the linear feedback shift register and a circuit under test which comprises a plurality of flip flop scan chains, wherein the outputs from the linear feedback shift register are provided to the scan chains. A first memory device stores flip flop deterministic state values for flip flops in each scan chain, and a multiplexer arrangement routes the flip flop deterministic state values to the scan chains in preference to the linear feedback shift register output. This structure enables flip flop deterministic state values to be supplied to the scan chains, bypassing the LFSR. This means that these flip flop values can assumed to have the required outputs when calculating the LFSR seed value for a particular test pattern, and this simplifies the equations used to generate the initial seed value for the LSFR.

Bist integrated circuit testing

To further develop a circuit arrangement (100; 100'), and in particular an application circuit, that is arranged to generate at least one test pattern, and a method of testing and/or diagnosing the circuit arrangement (100; 100') in such a way that reliable fault detection is ensured, it is proposed that the test pattern be remodelable and/or extendable into at least one presettable and/or deterministic test vector by means of at least one test pattern remodeling/extending element (10, 12, 14; 10', 12', 14'), and in that - the at least one test pattern remodeling/extending element (10, 12, 14; 10', 12', 14') is arranged, and in particular is inserted, upstream of at least one, and in particular upstream of each, branch point (52, 54, 56) on the at least one signal path (50).

Circuit arrangement and method of testing and/or diagnosing the same

Arrangement for testing an integrated circuit that comprises at least two circuit parts (1, 2) that in normal operation have different clock signals. Accordingly: each integrated circuit is configured so that clock signals from test software can be individually switched on or off; a software model of the test circuit is provided; the test software firstly activates all clock signals and evaluates test results for circuit components; and the test software undertakes testing for a number of text cycles. The invention involves generation of X- signals with an X-generator for testing purposes.

Andreas Glowatz

Papers

Short Papers On Acceleration of SAT-Based ATPG for Industrial Designs

Arrangement and method of testing an integrated circuit

Bist integrated circuit testing

Circuit arrangement and method of testing and/or diagnosing the same

Test arrangement for an integrated circuit