An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Plasma-assisted atomic layer deposition (ALD) is an energy-enhanced method for the synthesis of ultra-thin films with A-level resolution in which a plasma is employed during one step of the cyclic deposition process. The use of plasma species as reactants allows for more freedom in processing conditions and for a wider range of material properties compared with the conventional thermally-driven ALD method. Due to the continuous miniaturization in the microelectronics industry and the increasing relevance of ultra-thin films in many other applications, the deposition method has rapidly gained popularity in recent years, as is apparent from the increased number of articles published on the topic and plasma-assisted ALD reactors installed. To address the main differences between plasma-assisted ALD and thermal ALD, some basic aspects related to processing plasmas are presented in this review article. The plasma species and their role in the surface chemistry are addressed and different equipment configurations, including radical-enhanced ALD, direct plasma ALD, and remote plasma ALD, are described. The benefits and challenges provided by the use of a plasma step are presented and it is shown that the use of a plasma leads to a wider choice in material properties, substrate temperature, choice of precursors, and processing conditions, but that the processing can also be compromised by reduced film conformality and plasma damage. Finally, several reported emerging applications of plasma-assisted ALD are reviewed. It is expected that the merits offered by plasma-assisted ALD will further increase the interest of equipment manufacturers for developing industrial-scale deposition configurations such that the method will find its use in several manufacturing applications.

/pdf/plasma-assisted-atomic-layer-deposition-basics-opportunities-1iqbq8cz04.pdf

Plasma-Assisted Atomic Layer Deposition: Basics, Opportunities, and Challenges

https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

Embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided. The example gas channel plate includes a heat exchange surface including a plurality of heat exchange structures separated from one another by intervening gaps. The example gas channel plate also includes a heat exchange fluid director plate support surface for supporting a heat exchange fluid director plate above the plurality of heat exchange structures so that at least a portion of the plurality of heat exchange structures are spaced from the heat exchange fluid director plate.

Process feed management for semiconductor substrate processing

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technologyexcellent
conformality and within wafer uniformity, no loading effectovercome the limitations in this domain of the standard
PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct
spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By
decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP)
integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported
for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the
PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

This paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu bonding using Cu pads of unequal size and surface topography for the top and bottom wafers. The use of SiCN dielectrics allows to obtain a high W2W bonding energy (> 2 J/m2) at low annealing temperature (250 °C). Excellent Cu-Cu bonding is obtained after annealing at 350 °C. A novel CMP process, resulting in a slightly protruding Cu top pad and a slightly recessed Cu bottom pad, is introduced. The difference in pad sizes, allows for the necessary W2W overlay bonding tolerances. Excellent resistivity and yield results are obtained across bonded 300 mm Si wafers for scaled 360 nm top pads bonded to 720 nm bottom pads at 1.44 μm pitch (25% bottom Cu density). Feasibility of smaller pitches has been demonstrated by successfully bonding 180 nm top pads to 540 nm bottom pads at 0.72 μm pitch.

Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

Purpose Adequate postoperative pain control in hand surgery is a multifactorial issue affecting patient satisfaction, outcomes, and safety. However, prescription opioid abuse is becoming an increasingly prevalent problem in the Unites States. The purpose of this study was to determine if there was a difference in pain levels or pill consumption when using nonopioids, ibuprofen (IBU) and acetaminophen (ACE), versus an opioid, oxycodone (OXY), after carpal tunnel release (CTR) performed exclusively under local anesthesia without sedation. Methods Patients scheduled for primary unilateral CTR under local anesthesia alone were randomized to receive 10 deidentified opaque capsules of either OXY 5 mg, IBU 600 mg, or ACE 500 mg after surgery. Both the patient and the surgeon were blinded to the distributed medication. Patients reported the worst pain experienced daily (0–10 scale), the number of pills consumed daily, and any adverse effects from postoperative days 0–5. Results Analgesic pill-type distribution between the 105 patients who completed the study was 37 OXY, 34 IBU, and 34 ACE. For the endoscopic CTR group, mean total pills consumed from the day of surgery through postoperative day 5 for OXY, IBU, and ACE were 2.9, 4.2, and 2.7, respectively. The average worst daily pain scores for all days for the OXY, IBU, and ACE groups were 2.8, 2.5, and 2.8, respectively. For the open CTR group, mean total pills consumed from the day of surgery through postoperative day 5 for OXY, IBU, and ACE were 3.7, 5.1, and 4.2, respectively. The average worst daily pain scores for all days for the OXY, IBU, and ACE groups were 3.4, 2.5, and 2.3, respectively. Four of 5 adverse events were reported by OXY group patients, but all were minor with no reoperations or readmissions. Conclusions We recommend using nonopioids such as ACE and IBU in the postoperative management after CTR surgery, and regardless of the medication prescribed, we advise prescribing no more than 5–10 pills after surgery. Type of study/level of evidence Therapeutic II.

Pain Management After Carpal Tunnel Release Surgery: A Prospective Randomized Double-Blinded Trial Comparing Acetaminophen, Ibuprofen, and Oxycodone

High performance 3D integration Systems need a higher interconnect density between the die than traditional µbump interconnects can offer. For ultra-fine pitches interconnect pitches below 5µm a different solution is required. This paper describes a hybrid wafer-to-wafer (W2W) bonding approach that uses Cu damascene patterned surface bonding, allowing to scale down the interconnection pitch below 5 µm, potentially even down to 1µm, depending on the achievable W2W bonding accuracy. The bonding method is referred to as hybrid bonding since the bonding of the Cu/dielectric damascene surfaces leads simultaneously to metallic and dielectric bonding. In this paper, the integration flow for 300mm hybrid wafer bonding at 3.6µm and 1.8µm pitch will be described using a novel, alternative, non-oxide Cu/dielectric damascene process. Optimization of the surface preparation before bonding will be discussed. Of particular importance is the wafer chemical-mechanical-polishing (CMP) process and the pre-bonding wafer treatment. Using proper surface activation and very low roughness dielectrics, void-free room temperature bonding can be achieved. High bonding strengths are obtained, even using low temperature anneal (250°C). The process flow also integrates the use of a 5µm diameter, 50µm deep via-middle through-silicon-vias (TSV) to connect the wafer interfaces to the external wafer backside.

Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process

This paper presents our approach to hybrid bond scaling to 1μm pitch and recent demonstration results. The direct wafer stacking of two Cu/SiCN surface is realized between slightly protruding Cu nano-pad on one wafer and slightly recessed, but larger, Cu nano-pad on the second wafer. The protruding nano-pad is tailored as smaller than the recessed nano-pad to compensate for the overlay tolerance in the wafer-to-wafer (W2W) bonding. To control the stability and performance of Cu nano-pad integration process, the intensive inline atomic force microscopy (AFM) and surface acoustic microscopy (SAM) characterization is used on various test structures before/after wafer bonding. The surface flatness should be less than 1 nm/μm to ensure void free bonding. This surface planarization is readily achieved for Cu pad densities up to 25%. Finally, we have demonstrated the high yield and low resistance performance across the 300mm wafer for hybrid bond pitches between 5 and 1μm.

Andy Miller

Papers

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

Pain Management After Carpal Tunnel Release Surgery: A Prospective Randomized Double-Blinded Trial Comparing Acetaminophen, Ibuprofen, and Oxycodone

Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process

Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding