An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Plasma-assisted atomic layer deposition (ALD) is an energy-enhanced method for the synthesis of ultra-thin films with A-level resolution in which a plasma is employed during one step of the cyclic deposition process. The use of plasma species as reactants allows for more freedom in processing conditions and for a wider range of material properties compared with the conventional thermally-driven ALD method. Due to the continuous miniaturization in the microelectronics industry and the increasing relevance of ultra-thin films in many other applications, the deposition method has rapidly gained popularity in recent years, as is apparent from the increased number of articles published on the topic and plasma-assisted ALD reactors installed. To address the main differences between plasma-assisted ALD and thermal ALD, some basic aspects related to processing plasmas are presented in this review article. The plasma species and their role in the surface chemistry are addressed and different equipment configurations, including radical-enhanced ALD, direct plasma ALD, and remote plasma ALD, are described. The benefits and challenges provided by the use of a plasma step are presented and it is shown that the use of a plasma leads to a wider choice in material properties, substrate temperature, choice of precursors, and processing conditions, but that the processing can also be compromised by reduced film conformality and plasma damage. Finally, several reported emerging applications of plasma-assisted ALD are reviewed. It is expected that the merits offered by plasma-assisted ALD will further increase the interest of equipment manufacturers for developing industrial-scale deposition configurations such that the method will find its use in several manufacturing applications.

/pdf/plasma-assisted-atomic-layer-deposition-basics-opportunities-1iqbq8cz04.pdf

Plasma-Assisted Atomic Layer Deposition: Basics, Opportunities, and Challenges

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Lithography is a field in which advances proceed at a swift pace. This book was written to address several needs, and the revisions for the second edition were made with those original objectives in mind. Many new topics have been included in this text commensurate with the progress that has taken place during the past few years, and several subjects are discussed in more detail. This book is intended to serve as an introduction to the science of microlithography for people who are unfamiliar with the subject. Topics directly related to the tools used to manufacture integrated circuits are addressed in depth, including such topics as overlay, the stages of exposure, tools, and light sources. This text also contains numerous references for students who want to investigate particular topics in more detail, and they provide the experienced lithographer with lists of references by topic as well. It is expected that the reader of this book will have a foundation in basic physics and chemistry. No topics will require knowledge of mathematics beyond elementary calculus.

Principles of Lithography

Reduction of the bit size in conventional magnetic recording media is becoming increasingly difficult due to the superparamagnetic limit. Bit patterned media (BPM) has been proposed as a replacement technology as it will enable hard disk areal densities to increase past 1 Tb in−2. Block copolymer directed self-assembly (BCP DSA) is the leading candidate for forming BPM due to its ability to create uniform patterns over macroscopic areas. Here we review the latest research into two different BCP DSA techniques: graphoepitaxy and chemoepitaxy (or chemical prepatterning). In addition to assessing their potential for forming high density bit patterns, we also review current approaches using these techniques for forming servo patterns, which are required for hard disk drive (HDD) operation. Finally, we review the current state of UV nanoimprint lithography, which is the favoured technique for enabling mass production of BPM HDDs.

https://iopscience.iop.org/article/10.1088/0022-3727/46/50/503001/pdf

Directed self-assembly of block copolymers for use in bit patterned media fabrication

We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm 1/2 pitch on 12NA lithography system Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1st or 2nd patterning step This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance For a single line and 135NA system, the model predicted 31nm variance with mask CDU and etch bias being the major contributors We achieved an experimental resolution of 32-nm 1/2 pitch on 12NA system, which equals 020k1 Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s) After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 25nm (3s) Best overlay results equaled scanner SMO capability of ~7nm (mean+3s)

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technologyexcellent
conformality and within wafer uniformity, no loading effectovercome the limitations in this domain of the standard
PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct
spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By
decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP)
integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported
for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the
PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

Using 193nm lithography at NA=0.75, the minimum pitch that can be obtained in a single exposure is 160nm for dark field structures that are used in single damascene interconnect processing.
In order to evaluate the critical electrical parameters for the smaller technologies, a double patterning scheme has been developed to obtain electrical structures at pitches from 140nm down to 100nm. This corresponds to k1-factors of 0.27 to 0.19 for dense trenches. The designs have been split up into two layers at more relaxed pitch (twice the final pitch). The first step consists in patterning a small semi-isolated trench at this more relaxed pitch. Because of the limited resist resolution for semi-isolated trenches, shrink techniques such as resist reflow or RELACS are needed. After etching this first layer into a low-k material or metal hard mask, planarization of the topography is critical before performing the second exposure. The second exposure is then identical to the first one, but overlay to the first layer is extremely critical in order to get a reasonable process window. In this paper, we illustrate the feasibility of the double patterning technique for early sub-65nm-node evaluation of low-k materials. The resolution and processing limits will be shown for single layer resist processing with RELACS shrink for 193nm lithography at NA=0.75. The planarization for the second photo is done using organic BARC. We will also quantify the overlay requirements to measured and introduced overlay errors.

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

The aberration monitor allows independent determination of spherical, coma, astigmatism and three point in a single experiment using existing equipment. The monitor consists of a circular phase object, with a diameter of approximately (lambda) /NA and a phase depth of (lambda) /2. Due to the relative large diameter, the image prints as a narrow ring into the resist. Without aberrations its contours are concentric circles. Aberrations deform the ring in a characteristic way. A detailed analysis of the ring shape through focus identifies the aberrations of the projection lens. A linear aberration model is compared with simulations. Experimental results of various aberrations are shown and ar correlated to line width measurements and interferometric lens data.

Novel aberration monitor for optical lithography

Double patterning lithography - either with two litho and etch steps or through the use of a sacrificial spacer layer, have
equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to
process control, metrology and integration, but seem feasible for the 32nm node.
In this paper, we report results in exploring CDU and overlay performance at 32nm 1/2 pitch resolution of two double
patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific
aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and
spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD
populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple
populations in order to meet comparable 10% CDU as in single exposure.
We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming
capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After
compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and
multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU
populations entangled overlay into CDU.

http://client.blueskybroadcast.com/SPIE/AL08/manuscripts/6924-7_Finders.pdf

Mireille Maenhoudt

Papers

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

Novel aberration monitor for optical lithography

Double patterning for 32nm and below: an update