An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A system and method of pushing user-selected data items from a host system to a user's mobile data communication device upon detecting the occurrence of one or more user-defined event triggers is provided. The user may then move (or file) the data items to a particular folder within a folder hierarchy stored in the mobile data communication device, or may execute some other system operation on the data item. Software operating at the mobile device and the host system then synchronizes the folder hierarchy of the mobile device with a folder hierarchy of the host system, and any actions executed on the data items at the mobile device are then automatically replicated on the same data items stored at the host system, thus eliminating the need for the user to manually replicate actions at the host system that have been executed at the mobile data communication device.

System and Method for Pushing Information from a Host System to a Mobile Data Communication Device

The invention features methods of making devices, or “platens”, having a high-density array of through-holes, as well as methods of cleaning and refurbishing the surfaces of the platens. The invention further features methods of making high-density arrays of chemical, biochemical, and biological compounds, having many advantages over conventional, lower-density arrays. The invention includes methods by which many physical, chemical or biological transformations can be implemented in serial or in parallel within each addressable through-hole of the devices. Additionally, the invention includes methods of analyzing the contents of the array, including assaying of physical properties of the samples.

Apparatus for assay, synthesis and storage, and methods of manufacture, use, and manipulation thereof

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

In one embodiment, a conductive interconnect ( 38 ) is formed in a semiconductor device by depositing a dielectric layer ( 28 ) on a semiconductor substrate ( 10 ). The dielectric layer ( 28 ) is then patterned to form an interconnect opening ( 29 ). A tantalum nitride barrier layer ( 30 ) is then formed within the interconnect opening ( 29 ). A catalytic layer ( 31 ) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer ( 30 ). A layer of electroless copper ( 32 ) is then deposited on the catalytic layer ( 31 ). A layer of electroplated copper ( 34 ) is then formed on the electroless copper layer ( 32 ), and the electroless copper layer ( 32 ) serves as a seed layer for the electroplated copper layer ( 34 ). Portions of the electroplated copper layer ( 34 ) are then removed to form a copper interconnect ( 38 ) within the interconnect opening ( 29 ).

Interconnect structure in a semiconductor device and method of formation

Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Method for making printed circuit boards with selectivity filled plated through holes

Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer and via holes are formed through the photoimageable dielectric over pads and conductors of the wiring layer. Holes are formed through the substrate and the photoimageable dielectric, walls of the via holes, and walls of the through holes are copper plated. The copper plating on the photoimageable dielectric is patterned of form an exterior wiring layer. Components and/or pins are attached to the surface of the circuitized substrate with solder joints to form a high density circuit board assembly.

Manufacturing circuit board assemblies having filled vias

Disclosed is a printed circuit board and a method of preparing the printed circuit board, The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Method of preparing a printed circuit board

An information handling system is provided which comprises: a metal enclosure; at least one circuit assembly positioned within said metal enclosure, said circuit assembly including a circuitized substrate having at least one dielectric interior layer including a first surface and at least one hole therein; means for providing electrical power to said circuitized substrate within said metal enclosure; a filler material, wherein said filler material substantially fills said at least one hole within said at least one dielectric interior layer; a first wiring layer positioned on said first surface of said at least one dielectric interior layer, wherein said first wiring layer substantially covers said at least one hole having said filler material therein, said first wiring layer assisting in retaining said filler material within said at least one hole in said at least one dielectric interior layer; a first dielectric photoresist layer positioned on said first wiring layer and on said first surface of said at least one dielectric interior layer, wherein said first dielectric photoresist layer also includes at least one hole therein, said filler material also substantially filling said at least one hole within said first dielectric photoresist layer; a second wiring layer positioned on said first dielectric photoresist layer; wherein said second wiring layer includes a plurality of conductive pads as part thereof; and at least one external component electrically coupled to said conductive pads of said second wiring layer.

Information handling system with circuit assembly having holes filled with filler material

Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Anilkumar C. Bhatt

Papers

Method for making printed circuit boards with selectivity filled plated through holes

Manufacturing circuit board assemblies having filled vias

Method of preparing a printed circuit board

Information handling system with circuit assembly having holes filled with filler material

Method for making a printed wiring board