An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Although a molecular monolayer is only a few nanometers thick it can completely change the properties of a surface. Molecular monolayers can be readily prepared using the Langmuir-Blodgett methodology or by chemisorption on metal and oxide surfaces. This Review focuses on the use of chemisorbed self-assembled monolayers (SAMs) as a platform for the functionalization of silicon oxide surfaces. The controlled organization of molecules and molecular assemblies on silicon oxide will have a prominent place in bottom-up nanofabrication, which could revolutionize fields such as nanoelectronics and biotechnology in the near future. In recent years, self-assembled monolayers on silicon oxide have reached a high level of sophistication and have been combined with various lithographic patterning methods to develop new nanofabrication protocols and biological arrays. Nanoscale control over surface properties is of paramount importance to advance from 2D patterning to 3D fabrication.

Engineering silicon oxide surfaces using self-assembled monolayers.

Micro- and nanopatterning techniques for organic electronic and optoelectronic systems.

This article reviews the properties, fabrication and assembly of inorganic semiconductor materials that can be used as active building blocks to form high-performance transistors and circuits for flexible and bendable large-area electronics. Obtaining high performance on low temperature polymeric substrates represents a technical challenge for macroelectronics. Therefore, the fabrication of high quality inorganic materials in the form of wires, ribbons, membranes, sheets, and bars formed by bottom-up and top-down approaches, and the assembly strategies used to deposit these thin films onto plastic substrates will be emphasized. Substantial progress has been made in creating inorganic semiconducting materials that are stretchable and bendable, and the description of the mechanics of these form factors will be presented, including circuits in three-dimensional layouts. Finally, future directions and promising areas of research will be described.

Semiconductor Wires and Ribbons for High- Performance Flexible Electronics

There is disclosed a process for electroless plating of a conductive metal layer onto the surface of a non-conductive substrate, in which the substrate surface is prepared for receiving a coating of activator using conventional methods, and the coating of activator is applied by contacting the substrate surface with a stabilized sensitizing solution comprising ions of at least one Group VIII and IB transition metal, preferably palladium chloride, stannous ions in a molar concentration in excess of that of the transition metal ions, an acid, and a buffering salt; followed by contacting the sensitized substrate surface with a noble metal activating solution to catalyze the substrate surface for subsequent electroless plating. The sensitized and activated substrate is then contacted with an aqueous dry film photoresist, which is then imaged and developed to form a predetermined electrical circuit pattern, using conventional methods. The cleaned and imaged substrate is then immersed in an acidic electroless nickel metal depositing solution, for a time, at a concentration, and at a temperature sufficient to prepare the substrate for subsequent pattern electroplating, said acidic electroless metal depositing solution comprising ions of nickel, a complexing agent, a reducing agent capable of reducing said metal ions to a metallic state in an acidic medium, provided that said reducing agent does not include formaldehyde or a formaldehyde generating composition, one or more stabilizers, and water.

Electroless plating process for the manufacture of printed circuit boards

Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Method for making printed circuit boards with selectivity filled plated through holes

A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

Two signal one power plane circuit board

Disclosed is a printed circuit board and a method of preparing the printed circuit board, The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Method of preparing a printed circuit board

Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an information handling system with increased performance due to shorter signal flight times due to the higher device density.

Manufacturing computer systems with fine line circuitized substrates

A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

Roy H. Magnuson

Papers

Method for making printed circuit boards with selectivity filled plated through holes

Two signal one power plane circuit board

Method of preparing a printed circuit board

Manufacturing computer systems with fine line circuitized substrates

Copper plated PTH barrels and methods for fabricating