In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Method of making a wire-based semiconductor device

This research paper presents the effect of working temperature on the I ON , I OFF and I ON /I OFF ratio of gate all around nanowire TFET. The (Silvaco) simulation tool has been used to investigate the temperature characteristics of a transistor. The working temperature range of this study is from -50 to 150 step-up 25 °C. The final results indicate that the negative effects of increasing working temperature of gate all around nanowire TFET due to decreasing of the I ON /I OFF ratio. Hence, the results for I ON /I OFF ratio vs. working temperature characteristics may lead to the use of TFET in electronic circuits with lowest possible working temperature to obtain higher I ON /I OFF ratio.

Temperature Impact on The ION/IOFF Ratio of Gate All Around Nanowire TFET

In this paper, a Junctionless TFET coupled with a wrap around gate structure is proposed to combine the advantages of Junctionless TFET and Gate all around FET. This structure offers better controllability thereby improving the Ion/Ioff ratio. The impact of variation of different device parameters like gate length, nanowire diameter and doping concentration on the performance parameters of the Junctionless gate all around TFET is analyzed. Junctionless architecture also contributes for ease of fabrication since there is no doping concentration gradient for specific regions. It has a low OFF-state current (1.9 × 10−16 A/μm), a high ON-state current (0.6 mA/μm), a high I on /I off ratio of 1012 and an average Subthreshold slope of 58 mV/dec.

Performance analysis of junctionless gate all around tunnel field effect transistor

We present a CMOS compatible p-type gate-all-around (GAA) vertical silicon nanowire tunneling field effect transistor (TFET) featuring Si0.8Ge0.2 source with silicon channel. Besides heterojunction on source side, the highly abrupt doping profile at source-to-channel junction is achieved by low temperature dopant segregation. The fabricated devices display subthreshold slope (SS) as low as 30mV/dec over one decade of drain current, which remains below 60 mV/dec over 3 decades. In addition, our TFET showed reasonable Ion/Ioff ratio of (10 4 ) and low drain induced barrier lowering (DIBL) of 40 mV/V.

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Arvind Soundarapandian

Papers

Vertical Nanowire Gate-All-Around p-type Tunneling Field-Effect Transistor With Si 0.8 Ge 0.2 /Si Heterojunction