This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by ionizing radiation exposure have diminished by aggressive semiconductor scaling, the question remains whether there may be unknown, potentially worse threats lurking in the deep submicron regime. This manuscript provides a basic overview of some of the materials, devices, and designs that are being explored or, in some cases, used today. An overview of radiation threats and how radiation effects can be characterized is also presented. Last, the paper provides a detailed discussion of what we know now about how modern devices and materials respond to radiation and how we may assess, through the use of advanced analysis and modeling techniques, the relative hardness of future technologies

Total-Ionizing-Dose Effects in Modern CMOS Technologies

As the technology progresses, interconnect delays have become bottlenecks of chip performance. 3D integrated circuits are proposed as one way to address this problem. However, thermal problem is a critical challenge for 3D IC circuit design. We propose a thermal-driven 3D floorplanning algorithm. Our contributions include: (1) a new 3D floorplan representation, CBA and new interlayer local operations to more efficiently exploit the solution space; (2) an efficient thermal-driven 3D floorplanning algorithm with an integrated compact resistive network thermal model (CBA-T); (3) two fast thermal-driven 3D floorplanning algorithms using two different thermal models with different runtime and quality (CBA-T-Fast and CBA-T-Hybrid). Our experiments show that the proposed 3D floorplan algorithm with CBA representation can reduce the wirelength by 29% compared with a recent published result from (Hsiu et al., 2004). In addition, compared to a nonthermal-driven 3D floorplanning algorithm, the thermal-driven 3D floorplanning algorithm can reduce the maximum on-chip temperature by 56%.

/pdf/a-thermal-driven-floorplanning-algorithm-for-3d-ics-2e7oixsujx.pdf

A thermal-driven floorplanning algorithm for 3D ICs

The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.

Single Event Transients in Digital CMOS—A Review

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

An overview is presented of total ionizing dose (TID) effects in MOS and bipolar devices from a historical perspective, focusing primarily on work presented at the annual IEEE Nuclear and Space Radiation Effects Conference (NSREC). From the founding of the IEEE NSREC in 1964 until ~1976, foundational work led to the discovery of TID effects in MOS devices, the characterization of basic charge transport and trapping processes in SiO2, and the development of the first generations of metal-gate radiation-hardened MOS technologies. From ~1977 until ~1985, significant progress was made in the understanding of critical defects and impurities that limit the radiation response of MOS devices. These include O vacancies in SiO2, dangling Si bonds at the Si/SiO2 interface, and hydrogen. In addition, radiation-hardened Si-gate CMOS technologies were developed. From ~1986 until ~1997, a significant focus was placed on understanding postirradiation effects in MOS devices and implementing hardness assurance test methods to qualify devices for use in space systems. Enhanced low-dose-rate sensitivity (ELDRS) was discovered and investigated in linear bipolar devices and integrated circuits. From ~1998 until the present, an increasing focus has been placed on theoretical studies enabled by rapidly advancing computational capabilities, modeling and simulation, effects in ultra-thin oxides and alternative dielectrics to SiO2, and in developing a comprehensive model of ELDRS.

Total Ionizing Dose Effects in MOS and Low-Dose-Rate-Sensitive Linear-Bipolar Devices

A new approach for modeling the radiation-induced charge distribution in shallow-trench isolation (STI) structures shows that much less charge is trapped near the top of the trench. We found that charges inside the STI oxide are pushed down by the vertical electric field coming from the positive gate bias, leaving much less total-dose-induced charge close to the top of trench. This nonuniformity significantly affects the measured leakage current.

Nonuniform total-dose-induced charge distribution in shallow-trench isolation oxides

The present work considers electrothermal simulation of LDMOS devices and associated nonequilibrium effects. Simulations have been performed on three kinds of LDMOS: bulk Si, partial SOI and full SOI. Differences between equilibrium and nonequilibrium modeling approaches are examined. The extent and significance of thermal nonequilibrium is determined from phonon temperature distributions obtained using a common electronic solution and three different heating models (Joule heating, electron/lattice scattering, phonon scattering). The results indicate that, under similar operating conditions, nonequilibrium behavior is more significant in the case of full SOI devices, where the extent of nonequilibrium is estimated to be twice that of the partial SOI device and four times that of the bulk device. Time development of acoustic phonon and lattice temperatures in the electrically active region indicates that nonequilibrium effects are significant for times less than 10 ns.

http://tplab.vuse.vanderbilt.edu/docs/raman03-SSE.pdf

Simulation of nonequilibrium thermal effects in power LDMOS transistors

Ion-induced degradation and catastrophic failures in high-voltage SiC junction barrier Schottky power diodes are investigated. The experimental results agree with earlier data showing discrete jumps in leakage current for individual ions and show that the boundary between leakage current degradation and a single-event-burnout-like effect is a strong function of linear energy transfer and reverse bias. TCAD simulations show high localized electric fields under the Schottky junction, and high temperatures generated directly under the Schottky contact, consistent with the hypothesis that the ion energy causes eutectic-like intermixture at the metal–semiconductor interface or localized melting of the silicon carbide lattice.

/pdf/single-event-burnout-of-sic-junction-barrier-schottky-diode-4kpemkadya.pdf

Single-Event Burnout of SiC Junction Barrier Schottky Diode High-Voltage Power Devices

Three-dimensional (3D) stacked integrated circuits (ICs) can significantly improve circuit performance and offer the promise of integrating various technologies (memory, logic, RF, mixed-signal, optoelectronics) within a single block. Lack of 3D design tools and heat dissipation from vertically stacked multiple layers are the crucial problems in their development. To address these issues, CFD Research Corporation (CFDRC) is developing methodologies and tools to analyze and assess coupled electrical and thermal performance of 3D ICs, including calculation of realistic full-chip thermal distributions and determining from them signal delay/distortion. Due to the stacking technology, extensive localized heating can occur. Analysis to minimize these hot spots using thermal vias is demonstrated. Our Python-script based framework allows to drive and control all the aspects of the 3D model building (directly from layouts), thermal simulations, and results extraction/post-processing. Hence, it is a good basis for coupling with Electronic Design Automation (EDA) systems. We present results of automated, fast, but detailed thermal simulations of 3D stacked integrated circuits. In addition, procedures for automatic extraction of reduced and compact thermal-resistance-based 3D models have been implemented. These techniques greatly reduce required computational time, and allow for very fast parametric modeling analysis of 3D IC design configurations and temperature extraction. From these thermal resistance models, equivalent SPICE netlists may be generated and used for independent or coupled thermal analysis.

Fast, automated thermal simulation of three-dimensional integrated circuits

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

https://radhome.gsfc.nasa.gov/radhome/papers/tns07_sutton.pdf

Ashok Raman

Papers

Nonuniform total-dose-induced charge distribution in shallow-trench isolation oxides

Simulation of nonequilibrium thermal effects in power LDMOS transistors

Single-Event Burnout of SiC Junction Barrier Schottky Diode High-Voltage Power Devices

Fast, automated thermal simulation of three-dimensional integrated circuits

An Evaluation of Transistor-Layout RHBD Techniques for SEE Mitigation in SiGe HBTs