Limited-angle torque motor (LATM) is a critical component to precisely drive the valve angle of an engine’s fuel metering apparatus and accurately measure the fuel flow, and research on it is of great significance. Thus, the LATM of a certain kind is regarded as the research object in this paper. Firstly, a Simscape-based LATM integrated physical modeling method is proposed, which can better demonstrate the real operational characteristics of a motor, compared with the current mathematical model. Secondly, a Proportional-Integral-Derivative (PID) parameter self-tuning method based on a constriction factor particle swarm optimization (CPSO) algorithm is broached since it is difficult to tune due to a large number of multi-loop cascade PID control parameters. Simulation and experimental results showed that the control performance increases by 40% in the triple closed-loop PID control system with a stronger disturbance rejection, simpler design, and quickly responds when compared with the previous empirical tuning method. The triple closed-loop PID control system comprises an angle loop + angle velocity loop + current loop and technically supports the engineering application design of motors.

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Integrated Physical Modeling and Optimal Control Method of Limited-Angle Torque Motor in Fuel Metering Apparatus

Using digital methods for the implementation of different pulse-with modulation (PWM) strategies on multilevel converters (MLCs) has become popular among researchers during the past decade due to ease of controllability and realization. Among digital platforms, field programmable gate arrays (FPGAs) stand out to achieve this purpose due to its advantages like high clock frequency and parallel processing capability. Extensive research reveals that there is a gap in the literature in terms of detailed implementation of level-shifted PWM (LS-PWM) schemes on FPGAs. Hence, the main purpose of this paper is to fill this gap in the literature by suggesting a FPGA based digital implementation of LS-PWM schemes for MLCs. VHDL is employed to realize the architectural details of LS- PWM in this study. A comparison is held in terms of resource utilization of different LS-PWM methods within FPGA and it is revealed by simulation that three main types of LS-PWM schemes are realized successfully on FPGA. 

Digital Implementation of Level-Shifted Pulse Width Modulation for Multilevel Converters

Trapezoidal reference-based single carrier pulse width modulation method for multilevel converters with novel FPGA implementation

Harmonic Mitigation in a Hybrid System Using Intelligent Control Methods

Minimum device usages of field programmable gate array (FPGA) verification of multilevel PWM inverter drive generation

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

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Asyraf Rongi

Papers

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model