A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS

This paper describes the techniques used in the design of a 12-bit 290MS/s two stage time interleaved (TI) SAR ADC that minimizes the sampling skew and gain mismatches between multiple high resolution cores without the need for background digital calibration. A timing scheme which allows sharing of a single reference buffer and optimal distribution of conversion time among MSB and LSB bits is used. Further optimization in power is achieved by use of a process, voltage and temperature (PVT) invariant asynchronous timing loop that avoids pessimistic margins and simplifies design. The ADC is implemented in TSMC 28HPM process and achieves high input frequency figure of merit (FoM) of 23fJ/conv-step. Its high frequency Schreier FoM is 165.3dB, which is the highest reported number at this sampling range. The architecture is extended towards implementation of a 12-bit 460MS/s ADC, where two such instances are interleaved to achieve FoM of 30fJ/conv-step and greater than 70dB SFDR.

Ayushi Kansal

Papers

A 23fJ/conv-step 12b 290MS/s time interleaved pipelined SAR ADC