We demonstrate theoretically that most of the observed transport properties of graphene sheets at zero magnetic field can be explained by scattering from charged impurities. We find that, contrary to common perception, these properties are not universal but depend on the concentration of charged impurities nimp. For dirty samples (250 × 1010 cm−2 < nimp < 400 × 1010 cm−2), the value of the minimum conductivity at low carrier density is indeed 4e2/h in agreement with early experiments, with weak dependence on impurity concentration. For cleaner samples, we predict that the minimum conductivity depends strongly on nimp, increasing to 8e2/h for nimp ≈ 20 × 1010 cm−2. A clear strategy to improve graphene mobility is to eliminate charged impurities or use a substrate with a larger dielectric constant.

/pdf/a-self-consistent-theory-for-graphene-transport-4667tgnxun.pdf

A self-consistent theory for graphene transport.

The projected rise in wireless communication traffic has necessitated the advancement of energy-efficient (EE) techniques for the design of wireless communication systems, given the high operating costs of conventional wireless cellular networks, and the scarcity of energy resources in low-power applications. The objective of this paper is to examine the paradigm shifts in EE approaches in recent times by reviewing traditional approaches to EE, analyzing recent trends, and identifying future challenges and opportunities. Considering the current energy concerns, nodes in emerging wireless networks range from limited-energy nodes (LENs) to high-energy nodes (HENs) with entirely different constraints in either case. In view of these extremes, this paper examines the principles behind energy-efficient wireless communication network design. We then present a broad taxonomy that tracks the areas of impact of these techniques in the network. We specifically discuss the preponderance of prediction-based energy-efficient techniques and their limits, and then discuss the trends in renewable energy supply systems for future networks. Finally, we recommend more context-specific energy-efficient research efforts and cross-vendor collaborations to push the frontiers of energy efficiency in the design of wireless communication networks.

/pdf/energy-efficient-design-techniques-in-next-generation-spcx7r4fhh.pdf

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Controller Area Network (CAN) is a popular and very well-known bus system, both in academia and in industry. CAN protocol was introduced in the mid eighties by Robert Bosch GmbH [7] and it was internationally standardized in 1993 as ISO 11898-1 [27]. It was initially designed to distributed automotive control systems, as a single digital bus to replace traditional point-to-point cables that were growing in complexity, weight and cost with the introduction of new electrical and electronic systems. Nowadays CAN is still used extensively in automotive applications, with an excess of 400 million CAN enabled microcontrollers manufactured each year [14]. The widespread and successful use of CAN in the automotive industry, the low cost associated with high volume production of controllers and CAN's inherent technical merit, have driven to CAN adoption in other application domains such as: industrial communications, medical equipment, machine tool, robotics and in distributed embedded systems in general. CAN provides two layers of the stack of the Open Systems Interconnection (OSI) reference model: the physical layer the data link layer and optionally an additional application layer (not standardized). Notice that CAN physical layer was not de ned in Bosch original speci cation, only the data link layer was de ned. However, the CAN ISO speci cation lled this gap and the physical layer was then fully speci ed. CAN is a message-oriented transmission protocol, i.e., it de nes message contents rather than nodes and node addresses. Every message has an associated message identi er, which is unique within the whole network, de ning both the content and the priority of the message. Transmission rates are de ned up to 1 Mbps. The large installed base of CAN nodes with low failure rates over almost two decades, led to the use of CAN in some critical applications such as Anti-locking Brake Systems (ABS) and Electronic Stability Program (ESP) in cars. In parallel with the wide dissemination of CAN in industry, the academia also devoted a large e ort to CAN analysis and research, making CAN one of the must studied eldbuses. That is why a large number of books or book chapters describing CAN were published. The rst CAN book, written in French by D. Paret, was published in 1997 and presents the CAN basics [36]. More implementation oriented approaches, including CAN node implementation and application examples, can be found in Lorenz

/pdf/controller-area-network-1kt6uptpuo.pdf

Controller area network

A two-dimensional quantum mechanical model is presented for calculating carrier transport in ultra-thin gate-all-around quantum wire transistor (GAAQWT) and carbon nanotube field effect transistor ...

Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method

The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant practical work to illustrate the material taught and is centered around a single design example of a drawing machine. The exercises are composed so that students can regard themselves as part of a design team where they undertake the complete design of their own particular section of the system. These design tasks range from algorithmic specification and transaction-level modeling (TLM) of the architecture down to describing the design at the register transfer level (RTL) with subsequent verification of their prototype on a field-programmable gate array (FPGA). With this approach, students are able to explore and gain experience of the different techniques used at each level of the design hierarchy and the problems in translating to the next level down. Throughout the module, there is emphasis on using industry standard tools for the modeling and simulation, leading to the use of the SystemC and Verilog hardware description languages and Cadence for the simulation environment.

/pdf/system-on-chip-design-and-implementation-3u2cmeypde.pdf

System-on-Chip Design and Implementation

Power Reduction by Clock Gating Technique

From the Publisher:
Verilog provides platforms for designs to be described at different layers of complexity, combine them in a seamless manner, test them at every stage and build up a bug-free design. This book guides readers towards mastering Verilog as an HDL and using it for design.

Design Through Verilog HDL

The scale and complexity of integrated circuit designs are ever expanding which makes the verification process increasingly difficult and progressively time consuming. This dictates the need for testbench architectures with generic verification components that are reusable and easily extendable across designs. The UVM can realize such testbench architectures with coverage driven verification environments useful for constrained random testing. This paper focus on the UVM based verification of SPI protocol according to the verification plan prepared after an exhaustive analysis of SPI functional specifications. The UVM testbench generates random vectors, drives the SPI module and compares the captured response with expected response using scoreboard mechanism to verify the SPI functionality. The testbench also validates the characteristic features of SPI by running appropriate test cases and reports coverage cumulatively at the end of each test. The simulation results are analyzed to evaluate the effectiveness of the proposed testbench.

UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol

A nearest neighbour tight binding approximation for analysing the I-V characteristics of ballistic CNTFETs is developed making use of the non-equilibrium green's function (NEGF) formalism. NEGF provides a matrix based computational since device description at the atomic level can be employed and multiple quantum phenomenon that are visible in real time can be effectively modelled. The proposed model involves zig-zag CNTs as the channel material with a 25nm channel length that uses a basis transformation to decouple the channel Hamiltonian. Temperature dependence on the output characteristics of CNTFETs with varying chirality is also studied. All simulations are carried out on MATLAB.

https://iopscience.iop.org/article/10.1088/1757-899X/149/1/012183/pdf

B. Bala Tripura Sundari

Papers

Power Reduction by Clock Gating Technique

Design Through Verilog HDL

UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol

Simulation of Carbon Nanotube Field Effect Transistors using NEGF

High Level Synthesis for Retiming Stochastic VLSI Signal Processing Architectures