The projected rise in wireless communication traffic has necessitated the advancement of energy-efficient (EE) techniques for the design of wireless communication systems, given the high operating costs of conventional wireless cellular networks, and the scarcity of energy resources in low-power applications. The objective of this paper is to examine the paradigm shifts in EE approaches in recent times by reviewing traditional approaches to EE, analyzing recent trends, and identifying future challenges and opportunities. Considering the current energy concerns, nodes in emerging wireless networks range from limited-energy nodes (LENs) to high-energy nodes (HENs) with entirely different constraints in either case. In view of these extremes, this paper examines the principles behind energy-efficient wireless communication network design. We then present a broad taxonomy that tracks the areas of impact of these techniques in the network. We specifically discuss the preponderance of prediction-based energy-efficient techniques and their limits, and then discuss the trends in renewable energy supply systems for future networks. Finally, we recommend more context-specific energy-efficient research efforts and cross-vendor collaborations to push the frontiers of energy efficiency in the design of wireless communication networks.

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Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Comparative analysis of various types of multipliers for effective low power

The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information. The needless switching of clock, during the HOLD phase of either ‘logic 1’ or ‘logic 0’, may be abolished using gated clock. In this paper, we have presented a new clock gating technique incorporating Leakage Control Transistor. The improvised technique is employed to trigger a D-Flip Flop using 90nm PTM technology at 1.1V power supply. We have observed an impressive reduction in power, delay and latency using the proposed gating logic, which has outsmarted the existing works. The simulation is also performed in smaller technology nodes such as 65nm, 45nm and 32 nm to notice the change in delay, dynamic power and static power of the circuit.

A 90 nm leakage control transistor based clock gating for low power flip flop applications

The rapid developments in IoT, wireless technology, and mobile computing devices imply that ubiquitous computing is not a far-off dream from the present. But while it is not wrong to assume that ubiquitous computing will be achievable and feasible in the future, the concept is still plagued by a very high number of limitations. These numerous limitations are mainly related to the device’s hardware, security concerns, and energy maintenance for each device, cost and usability of the ubicomputing environment, connectivity, and complex user interface. This paper has pinpointed these exact issues and limitations that are stopping Ubicomp from becoming a reality. Along with finding these issues, we have also researched and mentioned potential solutions to them, which are being rapidly developed. Additionally, we have discussed comparative study of these solutions and their limitations and what can be improved. Toward the end, we have added our suggestions on what can be done to overcome the obstacles for UbiComp, and the future possibilities for the technology. 

A Novel Survey on Ubiquitous Computing

Clock gating is one of the most popular techniques used in many synchronous circuits for reducing dynamic power dissipation and it is helpful for decreasing the ability of power wasted by digital circuits. The major power consuming in electronics product is the systems clock signal and it is responsible for transition state of the components and this typically leads to the switching power consumption. Several techniques are used to reduce power some of the developed techniques are power gating, clock gating, adiabatic logic etc,. In clock gating technique, the unwanted clock signal is deactivated or blocked and by this activity, low dynamic power consumption can be achieved. Summary of issues associated with above clock gating techniques are presented for the research community to enable them to take future research in the right direction.

G Swetha Sri Lakshmi

Papers

Power Reduction by Clock Gating Technique