algorithmics and modular computations, Theory of Codes and Cryptography (3).From an analytical 1. RE Blahut. Theory and practice of error control codes. eecs.uottawa.ca/∼yongacog/courses/coding/ (3) R.E. Blahut,Theory and Practice of Error Control Codes, Addison Wesley, 1983. QA 268. Cached. Download as a PDF 457, Theory and Practice of Error Control CodesBlahut 1984 (Show Context). Citation Context..ontinued fractions.

Theory and practice of error control codes

In this paper, a low-noise cascaded PLL is proposed where an integer-N digital bang-bang PLL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a ΔΣ fractional-N PLL to generate 2.55-to-3 GHz output. In order to minimize the jitter of the 800 MHz clock, a reference injection scheme using dual-pulse ring oscillator is employed. Quantization noise from the delta-sigma modulator is suppressed without any noise cancellation techniques owing to the high operating frequency of the fractional-N PLL. Prototype implemented in 0.13 μm CMOS process achieves the worst-case RMS jitter of 356 fsrms over 100 Hz to 40 MHz integration bandwidth, while consuming 14.2 mW from a 1.2 V supply. The worst-case fractional spur measured over 7 different chips is -53.9 dBc and the reference spur is -84 dBc.

A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 $\mu$ m CMOS

A reduced complexity digital multi-stage noise shaping (MASH) delta-sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to ldquo1;rdquo shorter words are used in subsequent stages. Experimental results confirm simulations.

Reduced Complexity MASH Delta–Sigma Modulator

In this two-part paper, a design methodology for hardware reduction in digital delta-sigma modulators (DDSMs) based on bus-splitting and error masking is presented. Part I addresses Multi stAge noise SHaping (MASH) DDSMs with constant inputs; Part II focuses on error feedback modulators (EFMs) with time-varying inputs. In this paper, we address EFMs with DC inputs plus additive input least significant bit (LSB) dithering and show how hardware reduction can be achieved with minimal degradation of the output spectrum. We also address EFMs with sinusoidal inputs and show how bus-splitting and error masking techniques can be used to obtain a trade-off between the modulator complexity and the achievable signal-to-noise ratio.

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Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking—Part II: Non-Constant Input

Low-power low-loop-bandwidth (BW) integer-N frequency synthesizers with low phase noise have been reported previously. However, achieving similar power/phase-noise performance for a fractional-N synthesizer with a wide loop BW along with excellent spur performance has been challenging. A conventional fractional-N synthesizer is clocked by a crystal oscillator operating at a reference frequency (fref) less than a few tens of megahertz. An attractive alternative is to replace the low-frequency crystal oscillator with an integer-N phase-locked loop operating at an fref of a few hundreds of megahertz. The advantages and challenges of designing such a wide-loop-BW fractional-N synthesizer for low phase noise, spur, and power consumption are considered, and an extended-phase-range type-I ΣΔ fractional-N frequency synthesizer is implemented with an optimal fref of 290 MHz. Measurement results show that the synthesizer operating at 2.4 GHz with a wide loop BW of 1.8 MHz attains an in-band phase noise of -110 dBc/Hz and a worst case fractional spur of -69 dBc. The digital-intensive 0.18-μm CMOS design consumes 14.1 mW. No quantization noise cancellation or charge pump linearization techniques are used.

A 2.4-GHz Extended-Range Type-I $\Sigma\Delta$ Fractional- $N$ Synthesizer With 1.8-MHz Loop Bandwidth and $-$ 110-dBc/Hz Phase Noise

A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented The high-performance modulator, which consists of two sub-blocks, has a single-bit output making it best for this sort of application A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 07 of the full scale (07 FS) with an oversampling ratio of 167 The post-layout simulation of the digital circuit using 025 /spl mu/m CMOS technology predicts a maximum operating frequency of over 60 MHz at a supply voltage of 15 V

Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications

With increasing order of quadrature amplitude modulation (QAM), the bandwidth efficiency is improved in digital communication. However, in practice, the modulation order is limited, since conventional digital carrier recovery (CR) algorithms give rise to unacceptable phase error. The authors present an efficient software-aided technique for phase error reduction in CR for high-order QAM, based on the simple and well-known fourth power CR loop. Analytical and simulation results indicate that the new technique has several attractive features such as approximate of invariance of phase error improvement over modulation order and low hardware complexity for modulation orders as high as 256-QAM. Experimental results for 64 and 256-QAM illustrate phase error variance of less than −110 dBc/Hz at the frequency offset of 10 kHz, that is, 30 dB reduction of phase error variance or 3 dB increase in system processing gain compared to the conventional fourth power CR loop. This allows a significant improvement of bandwidth efficiency by increasing the modulation order, at the cost of slight complexity overhead.

Design and analysis of a reduced phase error digital carrier recovery architecture for high-order quadrature amplitude modulation signals

In this paper, a new technique for the OFDM timing synchronization problem under the multi-path channel conditions is presented. The algorithm exploits a pseudo-noise sequence instead of the duplicated version of OFDM frame tail as the guard interval. Different techniques are used to reduce the potential ISI caused by this operation. To evaluate the efficiency, the results of the simulations for the proposed technique and the conventional approaches are compared. The results reveal that the proposed technique has almost the same performance of overall transceiver link in addition to better timing synchronization compared to those of the conventional scheme.

A new preamble-less timing synchronization method for OFDM systems under multi-path channels

In this paper a new architecture for reducing the phase noise of digital carrier recovery (CR) algorithms is proposed. This architecture is useful for high-order QAM modulations in which very fine phase noise characteristic is needed for RF oscillators and for IF digital down converters (DDC). Using software aided algorithm, this architecture can be utilized in all digital CR algorithms to enhance their equivalent phase noise, making them almost independent of their loop filter performance. Simulations show a phase noise enhancement of about 20 dB compared to basic CR algorithms, allowing the designers to use simpler phase estimations techniques for demodulators.

A New Architecture for Reducing Phase Noise of Digital Carrier Recovery Algorithms in High-Order QAM Demodulators

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors or to reduce the signal to noise ratio requirement in transmission process. This paper presents an area-efficient 8-error correcting RS (255,239) decoder architecture using RiBM algorithm, implemented on a 0.25-?m CMOS technology with a supply voltage of 2.75 V. The total number of gates is about 12,600, which illustrates about an order of magnitude reduction compared to existing RS decoders. This improvement in hardware complexity is due to using a low complexity multiplier over GF (28) and constant multipliers. The decoder has a data processing rate of 1.6 Gbits/s at a clock frequency of 200 MHz.

B. Bornoosh

Papers

Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications

Design and analysis of a reduced phase error digital carrier recovery architecture for high-order quadrature amplitude modulation signals

A new preamble-less timing synchronization method for OFDM systems under multi-path channels

A New Architecture for Reducing Phase Noise of Digital Carrier Recovery Algorithms in High-Order QAM Demodulators

A Low Complexity VLSI Architecture for Reed-Solomon Decoder