We discuss non-volatile memories (NVM) for space applications. The focus will be both on technologies and devices aimed at the mainstream commercial markets and on rad-hard devices. Commercial NVMs are very attractive for space designers due to their large size (tens of Gbits), even though they have several issues related to ionizing radiation. Rad-hard NVMs offer radiation hardness, but are available only in small size (few Mbits). Most of the emphasis in this review paper will be on the current dominant technology in the mainstream market: floating gate flash memories. A comprehensive discussion of total dose and single event effects results for a wide cross section of NVMs will be presented. Finally, we will conclude with a cursory glance at other emerging non-volatile technologies.

Present and Future Non-Volatile Memories for Space

A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

Semiconductor device and method of manufacturing the same

In this paper, bottom-oxide thickness (Tbo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with Tbo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor

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Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.

Vertical channel type nonvolatile memory device and method for fabricating the same

This paper investigates total ionization dose (TID) effects on the electrical characteristics of Al2O3-/HfO2-/Al2O3-based charge trapping memory (CTM) devices by 10-keV X-ray. The Al2O3 layers serve as tunnel and blocking oxides, respectively, while HfO2 layer acts as charge-trapping layer. The C–V curves in pristine state shifted toward negative direction, but dc memory window almost kept the same after irradiation. Storage electrons decreased significantly with accumulated dose and reached approximately the same final value regardless of initial values. The impact of TID irradiation on program and erase conditions is also investigated. The program ability still worked well, but the erase ability disappeared gradually after irradiation. The physical mechanisms triggered by TID irradiation on Al2O3-/HfO2-/Al2O3-based CTM structure are discussed in detail with energy band diagrams.

Total Ionization Dose Effects on Charge-Trapping Memory With Al 2 O 3 /HfO 2 /Al 2 O 3 Trilayer Structure

We present recent results on an integrated radiation-hardened technology, which consists of scaled silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) and bulk CMOS devices - devices designed specifically for high-density, 1 Mb EEPROMs operating in space and military environments. These devices operate at low-voltage (+7V, 2.5 ms write, -7V, 7.5 ms erase) with 10-year retention at 150C and greater than 10/sup 5/ erase/write cycles. We describe erase/write, retention and endurance results over a 22-250C temperature range with a tunnel oxide of 1.8 nm, 'oxynitride' of 6.5 nm, and a blocking or 'cap' oxide of 3.0 nm. These scaled SONOS devices exhibit an extrapolated 10-year memory window of 1.2V (22C) and acceptable 0.3V (150C). A SONOS retention model is presented, which includes charge loss from both direct tunneling and thermal excitation. We discuss recent results of a radiation-hardened 1Mb SONOS EEPROM and its memory cell. In addition, we discuss experiments on 'localized' charge storage with hot electron injection to write SONOS/NROM/spl trade/ memory devices for higher functional density with increased retention.

Characterization of scaled SONOS EEPROM memory devices for space and military systems

This paper presents the experimental characteristics of 3-state n-MOS inverters utilizing Quantum Dot Gate (QDG) FETs. By employing FETs that have quantum dots in the gate region, particularly Si-SiOx cladded quantum dots and Ge-GeOx cladded quantum dots, intermediate states were observed in both variations of the device, both of which using the same architecture and mask set.

Quantum Dot Gate (QDG) FETs to Fabricate n-MOS Inverters Exhibiting 3-State Logic

This paper presents experimental results of nMOS quantum dot gate field effect transistor (QDGFET) based inverter devices for SRAM devices. A three-state inverter device was fabricated and tested with Si/SiO2 quantum dots. The work performed here builds off previous works performed with Si/SiO2 dot-based inverters which used two layers of quantum dots. This research explores multi-state SRAM device operation. A three-state (Si QDs) and a four-state (Si and Ge QDs) inverter are described, and they will allow for multistate logic devices to be utilized in everyday logic chips, which will require less devices to perform the same tasks as conventional devices, double the capacity of the device, and require less power, which will generate less of a thermal footprint. The data of the Half Cell SRAM, comprised of one access transistor and an inverter along with a capacitor, is presented here.

Fabrication and Characterization of nMOS Inverters Utilizing Quantum Dot Gate Field Effect Transistor (QDGFET) for SRAM Device

This paper investigates the underlying physics of a SRAM device utilizing three-state Quantum Dot Gate (QDG) FETs by building up the physics from the general QDG-FET, its relation to the QDG-Inverter, and ultimately, the QDG-SRAM. The resulting equations from the exploration of the device physics were utilized to create a simulation within SIMULINK. From the simulation, it was found that in addition to being able to store the “1” and “0” states that are customary for an SRAM device, there is also the ability to store an intermediate state and a pseudo-state as a result of the intermediate state, allowing for the possibility of a 2-bit SRAM device in the same spatial constraints of a conventional SRAM unit cell. Additionally, the experimental results of the QDG-SRAM half-cell and the implications of utilizing a 4 state device to create either a 4 state SRAM cell or a 6 state SRAM cell with two pseudo-states are also discussed.

QDG-SRAM Simulation Using Physics-Based Models of QDG-FET and QDG-Inverter

New methods for injecting and tunneling holes and electrons into the nitride charge storage layer in non-volatile semiconductor memory (NVSM) devices were investigated. These devices store holes and electrons in traps in a nitride layer in the gate dielectric. The programming mechanisms are Fowler-Nordheim tunneling, channel hot electron (CHE) injection, hot hole injection (HHI), and direct tunneling (DT). All measurements are performed on transistors with a gate dielectric composed of a 3.5 nm tunnel oxide, 1.5 nm silicon-nitride, and a 1.7 nm blocking oxide. Charge pumping measurements are employed to characterize the interface trap density of fresh devices and monitor the generation of the new interface traps during erase/write operations.

B.M. Khan

Papers

Characterization of scaled SONOS EEPROM memory devices for space and military systems

Quantum Dot Gate (QDG) FETs to Fabricate n-MOS Inverters Exhibiting 3-State Logic

Fabrication and Characterization of nMOS Inverters Utilizing Quantum Dot Gate Field Effect Transistor (QDGFET) for SRAM Device

QDG-SRAM Simulation Using Physics-Based Models of QDG-FET and QDG-Inverter

Characterizing damage to thin oxides induced during programming floating trap non-volatile semiconductor memory devices