Single-crystal silicon is being increasingly employed in a variety of new commercial products not because of its well-established electronic properties, but rather because of its excellent mechanical properties. In addition, recent trends in the engineering literature indicate a growing interest in the use of silicon as a mechanical material with the ultimate goal of developing a broad range of inexpensive, batch-fabricated, high-performance sensors and transducers which are easily interfaced with the rapidly proliferating microprocessor. This review describes the advantages of employing silicon as a mechanical material, the relevant mechanical characteristics of silicon, and the processing techniques which are specific to micromechanical structures. Finally, the potentials of this new technology are illustrated by numerous detailed examples from the literature. It is clear that silicon will continue to be aggressively exploited in a wide variety of mechanical applications complementary to its traditional role as an electronic material. Furthermore, these multidisciplinary uses of silicon will significantly alter the way we think about all types of miniature mechanical devices and components.

Silicon as a mechanical material

Transparent conductors—A status review

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

This paper presents a review of silicon micromachined accelerometers and gyroscopes. Following a brief introduction to their operating principles and specifications, various device structures, fabrication, technologies, device designs, packaging, and interface electronics issues, along with the present status in the commercialization of micromachined inertial sensors, are discussed. Inertial sensors have seen a steady improvement in their performance, and today, microaccelerometers can resolve accelerations in the micro-g range, while the performance of gyroscopes has improved by a factor of 10/spl times/ every two years during the past eight years. This impressive drive to higher performance, lower cost, greater functionality, higher levels of integration, and higher volume will continue as new fabrication, circuit, and packaging techniques are developed to meet the ever increasing demand for inertial sensors.

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Micromachined inertial sensors

Advancements in scaling gate insulators for MOS transistors permit low-voltage, silicon-oxide-nitride-silicon (SONOS) nonvolatile semiconductor memories (NVSMs) for a wide range of applications. The continued scaling of SONOS devices offers improved performance with a small cell size, single-level polysilicon with low voltage, fast erase/write, improved memory retention, increased endurance, and radiation hardness. In this article, we discuss scaled SONOS devices, SONOS memory technology, and some SONOS NVSM applications.

On the go with SONOS

The characterization of surface channel charge-coupled device line imagers with front-surface imaging, interline transfer, and 2-phase stepped oxide, silicon-gate CCD registers is presented. The analysis, design, and evaluation of 1/spl times/64 CCD line arrays are described in terms of their performance at low light levels. The authors describe the responsivity, resolution, spectral, and noise measurements on silicon-gate CCD sensors and CCD interline shift-registers. The influence of transfer inefficiency and electrical fat-zero insertion on resolution and noise is described at low light levels.

Characterization of surface channel CCD image arrays at low light levels

In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

A direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors. Charge transport in the erase/write mode of operation is interpreted in terms of the device threshold voltage shift. The threshold voltage shift in the erase/write mode is related to the amplitude and time duration of the applied gate voltage over the full range of switching times. MNOS memory devices ( X_{o}=25 \Aring, X_{N} = 335 \Aring ) exhibit a \Delta V_{th} = \plusmn3 V for an erase/write t_{p} = 100 ns, which corresponds to an initial oxide field strength E_{ox}= 1.2 \times 10^{7} V/cm. The direct tunneling theory is applied to the charge retention or memory mode in which charge is transported to and from the Si-SiO 2 interface states. The rate of charge loss to interface states is influenced by electrical stress which alters the interface state characteristics. We discuss the fabrication of complementary high-speed MNOS memory transistors and the experimental test procedures to measure charge transport and storage in these devices.

Characterization of thin-oxide MNOS memory transistors

The charge retention characteristics in scaled SONOS nonvolatile memory devices with an effective gate oxide thickness of 94 A and a tunnel oxide of 15 A are investigated in a temperature range from room temperature to 175°C. Electron charge decay rate is sensitive to the temperature, whereas hole charge decay rate remains essentially constant. Based on experimental observations and an amphoteric trap model for nitride traps, an analytical model for charge retention of the excess electron state is developed. Using this thermal activated electron retention model, the trap distribution in energy within the nitride film is extracted.

Marvin H. White

Papers

On the go with SONOS

Characterization of surface channel CCD image arrays at low light levels

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

Characterization of thin-oxide MNOS memory transistors

Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures