The authors describe a novel bipolar logic featuring a direct injection of minority carriers into the switching transistor. MTL is based on inverters having decoupled multicollector outputs for the logical combinations. The devices are self-isolated and no ohmic load resistors are required. This is a key to monolithic logic chips of very high functional density and low power dissipation. On experimental chips an excellent power-delay product of 0.35 pJ has been measured. These experiments show that a density of 100 gates/mm/SUP 2/ can be achieved with present manufacturing tolerances (minimum dimensions: 0.3-mil metal line width, 0.15-mil spacing, 0.2/spl times/0.2-mil/SUP 2/ contact holes).

Merged-transistor logic (MTL)-a low-cost bipolar logic concept

Integrated Schottky logic (ISL) is a new 200 mV voltage-swing LSI logic that can be made in standard Schottky processes with a double-layer metallization. It fills the gap between low-power Schottky TTL and I/SUP 2/L for those circuits where low-power Schottky TTL consumes too much power and takes up too much chip area, and when I/SUP 2/L does not attain the required speed. An ISL gate consists of a current source and a set of Schottky output diodes (wired AND gate). Minimum propagation delay times of 2.7 ns at 200 /spl mu/A/gate are obtained, with a speed-power product of 1.2 pJ. The packing density of ISL is 120 to 180 gates/mm/SUP 2/. The logic can be combined with ECL, I/SUP 2/L, and TTL on the same chip, and can also be made in analog processes.

ISL, a fast and dense low-power logic, made in a standard Schottky process

The advantages of using thin epitaxial layers for bipolar integrated circuits are discussed in this paper. Using epitaxial layer thicknesses of ~ 1 /spl mu/ and a low-voltage form of transistor-transistor logic, packing densities of 10/SUP 5/ logic gates/in/SUP 2/ have been achieved. The power x delay product of the circuits was 5 pJ. The transistors were formed in 1 /spl mu/ thick epitaxial layers and have inverse common-emitter current gains of 2 to 3. These high inverse gains make practical some new circuit configurations, including a dual-emitter inverter with reduced storage time. The thin epitaxial layer may be p type, rather than the usual n type, and this makes possible a new isolation scheme that allows the fabrication of bipolar integrated circuits using only five photolithographic steps.

Transistor-transistor logic with high packing density and optimum performance at high inverse gain

http://ieeexplore.ieee.org/iel5/5468992/5468993/05469050.pdf

ISL, A Fast and Dense Low-Power Logic, Made in a Standard Schottky Process

A study was made of the factors affecting the reliability of large-scale integrated (LSI) circuits. Particular attention was given to the effect on array reliability of the additional processing steps required to obtain multilevel metalization. The additional significant steps are low temperature deposition of a second dielectric layer on metalized LSI wafers, etching of vias through the second dielectric, and second level metalization. Consideration was also given to the effect of other trends in LSI, such as the use of smaller geometry and closer spacings. Possible new failure modes in multilevel arrays are: 1) shorts or increased leakage through or along deposited second layer dielectrics, 2) opens or increased series resistance in conductors, and 3) silicon surface effects. A review of literature on LSI was supplemented by results of a number of concurrent LSI programs and experimental studies. Test vehicles were designed to provide fundamental information about each of the categories of failure. Data obtained using these test vehicles to evaluate the multilevel metalized array structures are presented. A discussion concerning the merits and limitations of the specially designed test vehicles for process development, process control, and reliability tests is given. It is concluded that with the proper in-process controls, tests and screens, LSI arrays will be substantially more reliable per function accomplished than are conventional integrated circuits.

Failure mechanisms in large-scale integrated circuits

A new, simplified, bipolar integrated circuit structure is described. This structure eliminates the need for the conventional isolation diffusion. Isolation is accomplished with the collector diffusion. This results in fewer fabrication steps than are required in fabrication of the standard buried collector structure. In addition, the new structure has greater circuit packing density because of the smaller area required for isolation. Transistor-transistor logic circuits have been fabricated using the new structure. Using 5 µm masking tolerances and line widths, propagation delays of 5-7 ns have been obtained at a power dissipation of 4 mW while achieving circuit packing densities 2.5 times higher than obtainable using the standard buried collector structure with the same masking tolerances. Circuits formed using 2-3 µm tolerances and line widths resulted in propagation delays of 20 ns at 0.4 mW power dissipation.

Collector diffusion isolated integrated circuits

Base-diffusion isolation with a buried collector simplifies the fabrication of very-high-speed circuits. Base-diffusion isolation with a buried collector simplifies the fabrication of very-high-speed circuits. Base-diffusion isolation without a buried collector permits the fabrication of circuits with no more processing than is needed for a discrete planar transistor. Packing densities of these transistors are similar to those of IGFETs. Functional packing densities will depend upon the particular circuit used. The new structures should permit fabrication of many circuits with the performance advantages of bipolar devices at costs comparable to those of IGFETs. To exploit these devices to the best advantage low-voltage logic is required. Studies of an exploratory digital system using gates operated from a 2-V supply have shown the feasibility of such an approach.

New, simplified, bipolar technology and its application to systems

Performance/cost ratios greater than 1 MIP per central processing unit (CPU) $ will be realized. As design rules decrease, the traditional superiority of on-chip interconnections increases, transistor performance becomes ever less an issue, and single-chip microcomputers will dominate the whole computer industry. CMOS technology will take the lead for the foreseeable future because its low power dissipation permits the best possible performance-it provides more MIPs per watt than competing technologies. Design will be increasingly computer aided. Database management and verification can, on the other hand, be reduced to logical processes and assigned to machines. Symbolic designs, hierarchically organized and executed with logic, layout, and system design done in parallel, offer good packing densities and performance and permit reasonable design intervals. The Bellmac-32A microprocessor, a 0.7 W 1 MIP CMOS chip containing 146000 transistor sites, used the above strategies. Its control section, I/O, and much of its data path were designed and debugged in 14 months.

Microcomputers: trends, technologies, and design strategies

Microprocessors have created a revolution in the application of digital electronics. Although they are viewed within the industry as small-scale computers, to the user the microprocessor system affords a universal programmable component for many control and information-handling applications. However, to obtain the most satisfactory results, we should know which of the many architectures now appearing have the widest appeal; how desirable is it to have many alternative languages and hardware options; what will be the most widely-used technology, and how much will one need to know of the electronics of a chosen system.

http://ieeexplore.ieee.org/iel6/8290/25922/01155547.pdf

B. Murphy

Papers

Transistor-transistor logic with high packing density and optimum performance at high inverse gain

Collector diffusion isolated integrated circuits

New, simplified, bipolar technology and its application to systems

Microcomputers: trends, technologies, and design strategies

Microprocessor trends