In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.

Overview and status of metal S/D Schottky-barrier MOSFET technology

The performance limits of carbon nanotube field-effect transistors (CNTFETs) are examined theoretically by extending a one-dimensional treatment used for silicon metal–oxide–semiconductor field-effect transistors (MOSFETs). Compared to ballistic MOSFETs, ballistic CNTFETs show similar I–V characteristics but the channel conductance is quantized. For low-voltage, digital applications, the CNTFET with a planar gate geometry provides an on-current that is comparable to that expected for a ballistic MOSFET. Significantly better performance, however, could be achieved with high gate capacitance structures. Because the computed performance limits greatly exceed the performance of recently reported CNTFETs, there is considerable opportunity for progress in device performance.

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Performance projections for ballistic carbon nanotube field-effect transistors

We describe the implementation of a Monte Carlo model for electron transport in silicon. The model uses analytic, nonparabolic electron energy bands, which are computationally efficient and sufficiently accurate for future low-voltage s, 1V d nanoscale device applications. The electron-lattice scattering is incorporated using an isotropic, analytic phonon-dispersion model, which distinguishes between the optical/acoustic and the longitudinal/transverse phonon branches. We show that this approach avoids introducing unphysical thresholds in the electron distribution function, and that it has further applications in computing detailed phonon generation spectra from Joule heating. A set of deformation potentials for electron-phonon scattering is introduced and shown to yield accurate transport simulations in bulk silicon across a wide range of electric fields and temperatures. The shear deformation potential is empirically determined at Ju= 6.8 eV, and consequently, the isotropically averaged scattering potentials with longitudinal and transverse acoustic phonons are DLA= 6.39 eV and DTA= 3.01 eV, respectively, in reasonable agreement with previous studies. The room-temperature electron mobility in strained silicon is also computed and shown to be in better agreement with the most recent phonon-limited data available. As a result, we find that electron coupling with g-type phonons is about 40% lower, and the coupling with f-type phonons is almost twice as strong as previously reported. © 2004 American Institute of Physics . [DOI: 10.1063/1.1788838]

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Analytic band Monte Carlo model for electron transport in Si including acoustic and optical phonon dispersion

Nanoscale Schottky barrier MOSFETs (SBFETs) are explored by solving the two-dimensional Poisson equation self-consistently with a quantum transport equation. The results show that for SBFETs; with positive, effective metal-semiconductor barrier heights, the on-current is limited by tunneling through a barrier at the source. If, however, a negative metal-semiconductor barrier height could be achieved, on-current of SBFETs would approach that of a ballistic MOSFET. The reason is that the gate voltage would then modulate a thermionic barrier rather than a tunneling barrier, a process similar to ballistic MOSFETs and one that delivers more current.

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A computational study of thin-body, double-gate, Schottky barrier MOSFETs

Nanoscale Schottky barrier MOSFETs (SBFETs) are explored by solving the two-dimensional Poisson equation self-con- sistently with a quantum transport equation. The results show that for SBFETs with positive, effective metal-semiconductor barrier heights, the on-current is limited by tunneling through a barrier at the source. If, however, a negative metal-semiconductor barrier height could be achieved, on-current of SBFETs would approach that of a ballistic MOSFET. The reason is that the gate voltage would then modulate a thermionic barrier rather than a tunneling barrier, a process similar to ballistic MOSFETs and one that de- livers more current.

A Computational Study of Thin-Body, Double-Gate,

A full-band Monte Carlo model has been coupled to a Schrodinger equation solver to account for the size quantization effects that occur at heterojunctions, such as the oxide interface in MOS devices. The overall model retains the features of the well-developed semi-classical approach, by treating self-consistently the Schrodinger solution as a correction to the particle-based Monte Carlo. The simulator has been benchmarked by comparing results for MOS capacitors and double gate structures with a self-consistent quantum solution, showing that the proposed approach is efficient and accurate. This quantum correction methodology is extended to device simulation, by accounting for the interplay between confinement and transport through a parameter which we call "transverse" temperature. This approach appears to be valid even for nanometer-scale devices in which nonequilibrium ballistic transport is occurring. We present simulations of a 25-nm MOSFET and compare results obtained with and without the quantum correction.

A quantum correction based on Schrodinger equation applied to Monte Carlo device simulation

A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 /spl mu/m Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 /spl Aring/ gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage.

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Simulation of Schottky barrier MOSFETs with a coupled quantum injection/Monte Carlo technique

A fullband Monte Carlo simulator has been used to analyze the performance of scaled n-channel double-gate (DG) MOSFETs. Size quantization in the channel is accounted for by using a quantum correction based on Schrodinger equation. Scattering induced by the oxide interface is included with a model calibrated with measurements for bulk devices. The detailed self-consistent treatment of quantum effects leads to several interesting observations. We observe that the sheet charge in DG devices does not decrease as much as expected in bulk devices when quantum-mechanical effects are included. The average carrier velocity in the channel is also somewhat reduced by quantum effects, as a second-order effect. In the test cases studied here, application of quantum effects causes a reduction in simulated current not exceeding 15%. In a DG structure, quantum effects tend to concentrate the charge density in the center of the channel, where transverse fields are lower. Because of this, interface scattering appears to be less pronounced when quantum effects are included.

B. Winstead

Papers

A quantum correction based on Schrodinger equation applied to Monte Carlo device simulation

Simulation of Schottky barrier MOSFETs with a coupled quantum injection/Monte Carlo technique

Monte Carlo simulations of double-gate MOSFETs