Showing papers by "Baoxing Duan published in 2015"
TL;DR: In this article, a step doping buffered layer under the super junction LDMOS was proposed to obtain the low loss for the highvoltage region, which improved the breakdown voltage (BV) and average lateral electric field.
Abstract: A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by $\sim 50$ % than that of the conventional LDMOS, and improved by $\sim 32$ % than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/ $\mu $ m in the high-voltage region The experimental ${R} _{\mathbf {\mathrm{{\scriptstyle ON}},{\textrm sp}}}$ of the proposed SJ-LDMOS is 241 m $\Omega \,\cdot $ $\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with a BV of 368 V, breaking the silicon limit relationship for ${R} _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ of 71.8 m $\Omega ~\cdot ~\mathrm{cm}^{\mathrm {\mathbf {2}}}$ with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/ $R _{\mathrm{{\scriptstyle ON}},\textrm {sp}}$ is 15.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS.
64 citations
TL;DR: In this paper, a new superjunction lateral double-diffused MOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) has been proposed, for the first time, with the complete three-dimensional reduced surface field (3D-RESURF).
Abstract: A new superjunction lateral double-diffused MOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) has been proposed in this letter, for the first time, with the complete three-dimensional reduced surface field (3D-RESURF). The SIPOS SJ-LDMOS along the three dimensions are subject to the electric field modulation, which achieves the complete 3D-RESURF effect. The simulated breakdown voltage (BV) for the unit length of the drift region is improved to 19.4 $\mathrm {V}/ \mu \text{m}$ . The drift region with the high concentration compared with the conventional LDMOS can be depleted completely in the OFF-state to obtain the high BV. Moreover, the majority carrier accumulation can be formed to further decrease $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ (specific on resistance) during the ON-state operation. Three effects have been combined to SIPOS SJ-LDMOS for the superjunction ideal, electric field modulation and the majority carrier accumulation by SIPOS. The tradeoff between the BV and $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ has been improved to break through the silicon limit. The results show that the experimental $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ of SIPOS SJ-LDMOS is 18 $\text{m}\Omega \cdot \textrm {cm}^{2}$ with the tested BV of 376 V, which is less than that of 31.1 $\text{m}\Omega \cdot \textrm {cm}^{2}$ for the $N$ -buffer SJ-LDMOS with the simulated BV of 287 V, and far less than 71.8 $\text{m}\Omega \cdot \textrm {cm}^{2}$ for the conventional LDMOS with the simulated BV of 254 V for the same drift region length of 20 $\mu \text{m}$ .
31 citations
TL;DR: In this paper, a novel 4H-SiC metal semiconductor field effect transistor with ultrahigh upper gate (UU-MESFET) by depletion layer variation and electric field modulation is proposed for the first time.
9 citations