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Bartholomew Blaner

Researcher at IBM

Publications -  100
Citations -  1724

Bartholomew Blaner is an academic researcher from IBM. The author has contributed to research in topics: Cache & Instructions per cycle. The author has an hindex of 25, co-authored 100 publications receiving 1703 citations.

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IBM POWER7 multicore server processor

TL;DR: The processor core and caches of the POWER7 processor chip are significantly enhanced to boost the performance of both single-threaded response-time-oriented, as well as multithreaded, throughput-oriented applications.
Patent

Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit

Abstract: The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
Patent

Data dependency collapsing hardware apparatus

TL;DR: A multi-function ALU for use in digital data processing is described in this paper, which facilitates the execution of instructions in parallel, thereby increasing processor performance, and reduces the instruction execution latency that results from data dependency hazards in a pipelined machine.
Patent

Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode

TL;DR: In this article, a multifunction permutation switch, in a cyclic mode of operation, connects the input bit lines to the output bit lines so that the sequence of input bits are maintained on the output bits when the bits on the input lines are considered as arranged in a circle.
Patent

Multiple condition code branching system in a multi-processor environment

TL;DR: In this article, a data processing system includes a number of processing elements wherein each of the processing elements generates one or more condition signals, one memory element associated with the processing element for storing instructions and data associated with processing elements, at least one register for storing a predicate associated with each predicate, and logic for comparing condition signals from each processing element with a corresponding predicate.