Dung Quoc Nguyen

TL;DR: The processor core and caches of the POWER7 processor chip are significantly enhanced to boost the performance of both single-threaded response-time-oriented, as well as multithreaded, throughput-oriented applications.

TL;DR: The core microarchitecture innovations made in the POWER8 processor, designed to significantly improve both single-thread performance and single-core throughput over its predecessor, the POWER7® processor, are described.

TL;DR: Recovery circuits as discussed by the authors remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system, by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core.

TL;DR: In this paper, a method and apparatus for dispatch group checkpointing in a microprocessor are provided, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion.

TL;DR: In this paper, the issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue and determines that the unified payload does not include a load-store instruction.