B
Been-Yih Jin
Researcher at Intel
Publications - 55
Citations - 2142
Been-Yih Jin is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 26, co-authored 55 publications receiving 2142 citations.
Papers
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Patent
Nonplanar device with stress incorporation layer and method of fabrication
TL;DR: In this paper, a semiconductor device consisting of a top surface and laterally opposite sidewalls is formed on an insulating substrate, where a gate dielectric layer is created on the top surface of the semiconductor body.
Patent
CMOS devices with a single work function gate electrode and method of fabrication
TL;DR: In this paper, a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering is described.
Patent
Non-planar MOS structure with a strained channel region
TL;DR: In this article, a non-planar MOS transistor with a strained channel region is described. But the authors do not consider the effect of a planar MISO transistor with an unstrained channel region.
Patent
Two-dimensional condensation for uniaxially strained semiconductor fins
TL;DR: In this paper, techniques for enabling multi-sided condensation of semiconductor fin-based transistors are described, where a fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion.
Patent
Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
TL;DR: In this paper, a nonplanar tri-gate p-MOS transistor structure with a strained channel region and a non-planar Tri-gate integrated strained complimentary metaloxide-semiconductor (CMOS) structure is described.