For the first time to the best of our knowledge, this paper provides an overview of millimeter-wave (mmWave) 5G antennas for cellular handsets. Practical design considerations and solutions related to the integration of mmWave phased-array antennas with beam switching capabilities are investigated in detail. To experimentally examine the proposed methodologies, two types of mesh-grid phased-array antennas featuring reconfigurable horizontal and vertical polarizations are designed, fabricated, and measured at the 60 GHz spectrum. Afterward the antennas are integrated with the rest of the 60 GHz RF and digital architecture to create integrated mmWave antenna modules and implemented within fully operating cellular handsets under plausible user scenarios. The effectiveness, current limitations, and required future research areas regarding the presented mmWave 5G antenna design technologies are studied using mmWave 5G system benchmarks.

Millimeter-Wave 5G Antennas for Smartphones: Overview and Experimental Demonstration

This paper describes a 28-GHz CMOS direct conversion transceiver with packaged $2 \times 4$ patch antenna array for 5G communication. Beamforming antenna and reconfigurable transceiver architecture are used for high effective isotropic radiated power (EIRP). For low error vector magnitude (EVM), switchless matching transmitter (Tx)/receiver (Rx) to antenna and 28-GHz injection-locked local oscillator (LO) generator are employed. Test chip was fabricated in 28-nm RF CMOS process. Measurement results show Tx EIRPsat of 31.5 dBm ( $P_{\mathrm {sat}}$ of 10.5 dBm in one power amplifier (PA)), EIRPmax 24 dBm ( $P_{\mathrm {max}}$ of 2 dBm with backoff of 7.5 dB in one PA), Rx noise figure of 6.7 dB, and integrated LO phase noise of −38.7 dBc (0.67°). After IQ mismatch calibration, Tx LO leakage and image power are less than −35 dBc. Rx and Tx EVM show 2.2% (−33 dB) at medium RF power (Rx $P_{\mathrm {in}}$ of −60 dBm and Tx EIRP of 0 dBm) with well-fit beam control capability.

A 28-GHz CMOS Direct Conversion Transceiver With Packaged $2 \times 4$ Antenna Array for 5G Cellular System

This paper describes a 28GHz CMOS direct conversion transceiver with packaged 2×4 patch antenna arrays for 5G communication. Test results show good RF performances of Rx NF 6.7dB, Maximum Tx EIRP 31.5dBm (1PA P out_sat =10.5dBm), LO integrated phase noise −37.8dBc (0.67°), Rx/Tx EVM around 2.2% (−33.1dB) at mid RF power, and well-fitted beam control capability.

A 28GHz CMOS direct conversion transceiver with packaged antenna arrays for 5G cellular system

This paper presents a “fully-connected” hybrid beamforming receiver that independently weights each element in an antenna array prior to separate downconversion chains that output independent baseband streams. A receiver architecture is introduced, which implements RF-domain complex-valued Cartesian weighting, RF-domain combining, and multi-stream heterodyne complex-quadrature downconversion. Each RF-domain Cartesian weight is implemented by a pair of 5-bit digitally controlled programmable-gain amplifiers, whose outputs are combined with the weighted signals from other antennas prior to complex-quadrature downconversion. Signal combination is performed by a wideband small-footprint distributed active combiner. A 25–30 GHz hybrid beamforming receiver with eight antenna inputs and two baseband output streams is designed in 65-nm CMOS. In each antenna path, the receiver achieves 34-dB conversion gain, 7.3-dB minimum noise figure, and 5 GHz of RF bandwidth. The entire receiver consumes 340 mW (equivalent to 27.5 mW per antenna per stream) including low-noise amplification, RF-domain beamforming, multi-stream downconversion, and local oscillator generation and distribution circuitry. The receiver occupies 3.86 mm2 excluding pads, equivalent to 0.36 mm2 per antenna per stream. Single-element characterization results are presented, along with characterization of several spatial processing techniques including interference cancellation (20 dB peak to null for two elements), simultaneous two-stream reception, and adaptive-codebook-search-based beam acquisition.

A 25–30 GHz Fully-Connected Hybrid Beamforming Receiver for MIMO Communication

This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA’s output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation. And the coupling coefficient ( $k$ ) of the MCR can be determined from the no gain ripple condition. Fabricated in 65-nm CMOS process, the PA chip achieves 32.9% peak power added efficiency, 15.3-dBm saturated output power ( $P_{\mathrm {sat}}$ ), and 12.9-dBm output 1-dB compression point ( $P_{\mathrm {1\,dB}}$ ). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz).

A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS

This paper presents a 28-GHz four-channel phased-array receiver in 130-nm SiGe BiCMOS technology for fifth-generation cellular application. The phased-array receiver employs scalar-only weighting functions within each receive path and then global quadrature power combining to realize beamforming. We discuss both the theory and nonidealities of this architecture and then circuit design details for our phased-array front-end prototype. Differential low-noise amplifiers and dual-vector variable-gain amplifiers are used to realize each front end in a compact area of 0.3 mm2. Across 4-b phase settings, each array element achieves 5.1–7 dB noise figure, −16.8 to −13.8 dBm input-referred 1-dB compression point, and −10.5 to −8.9 dBm input-referred third-order intercept point. The average gain per element is 10.5 dB at 29.7 GHz, whereas the 3-dB bandwidth is 24.5% (26.5–33.9 GHz). Root-mean-squared gain and phase errors are less than 0.6 dB and 5.4° across 28–32 GHz, respectively, and all four elements provide well-matched and well-isolated responses. Power consumption is 136 mW per element, equaling 546 mW for the four-element array.

A 28-GHz Phased-Array Receiver Front End With Dual-Vector Distributed Beamforming

This paper presents a 28-GHz four-channel phased-array receiver in 120-nm SiGe BiCMOS technology for 5G cellular application. The phased-array receiver employs scalar-only weighting functions within each front-end and then global quadrature power combining to realize beamforming. Differential LNAs and dual-vector variable-gain amplifiers are used to realize each front-end with compact area. Each front-end achieves 5.1 to 7 dB noise figure, −16.8 to −13.8 dBm input compression point, −10.5 to −8.9 dBm input third-order intercept point across 4-bit phase settings and a 3-dB bandwidth of 26.5 to 33.9GHz, while consuming 136 mW per element. RMS gain and phase errors are < 0.6 dB and < 5.4° at 28–32 GHz respectively, and all four elements reveal well-matched responses.

A 28-GHz 4-channel dual-vector receiver phased array in SiGe BiCMOS technology

Provided herein are apparatus and methods for radio frequency (RF) switching. In certain configurations, an RF switching circuit includes two or more FETs electrically connected in series between an input terminal and an output terminal, with the two or more FETs in the series connected via one or more intermediate nodes. The RF switching circuit receives a first switch control signal that can be used to control the DC bias voltages of the gates of the two or more FETs, and a second switch control signal that can be used to control the DC bias voltages of the one or more intermediate nodes.

Apparatus and methods for radio frequency switching

This paper presents a broadband, high-dynamic range, active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-n/fractional-n PLL to generate an LO signal with an in-band phase noise FOM of −223 dBc/Hz/Hz. The 100–3000MHz active mixer can be configured for up or down conversion. The mixer's linearity can be boosted from +25dBm to +29dBm by increasing the bias current, and optimized for a wide range of input frequencies through a variable capacitor setting. Designed in Si-Ge 0.25µm BiCMOS, the entire chip occupies 5.84mm2 and consumes 250mA from a 5V supply.

A 100-3000MHz, up/ down-convert, +29dBm IIP3, 13dB NF, active mixer with integrated fractional-N PLL and VCO

Apparatus and methods for switch-coupled oscillators are disclosed. In certain implementations, an oscillator system includes a primary oscillator, one or more auxiliary oscillators, one or more switching circuits, and an oscillator control circuit. The oscillator control circuit can be used to control the one or more switching circuits to selectively couple the primary oscillator to all or a portion of the one or more auxiliary oscillators. The oscillator control circuit can also disable any auxiliary oscillators that are decoupled from the primary oscillator to reduce power consumption. By selecting a number of auxiliary oscillators to couple to the primary oscillator, the oscillator system can have a configurable phase noise versus power consumption profile.

Benjamin Walker

Papers

A 28-GHz Phased-Array Receiver Front End With Dual-Vector Distributed Beamforming

A 28-GHz 4-channel dual-vector receiver phased array in SiGe BiCMOS technology

Apparatus and methods for radio frequency switching

A 100-3000MHz, up/ down-convert, +29dBm IIP3, 13dB NF, active mixer with integrated fractional-N PLL and VCO

Apparatus and methods for switch-coupled oscillators