In this paper, we propose a physics-based compact model of the pinned photodiode (PPD) combined with the transfer gate. A set of analytical expressions is derived for the 2-D electrostatic profile, the PPD capacitance, and the charge transfer current. The proposed model relies on the thermionic emission current mechanism, the barrier modulation, and the full-depletion approximation to obtain the charge transfer current. The proposed physics-based model is fully validated with technology computer-aided design simulations, i.e., stationary and optoelectrical simulations. The development of such a compact model for PPD represents an essential step toward the design, simulation, and optimization of PPD-based pixels in CMOS image sensors.

/pdf/compact-modeling-of-charge-transfer-in-pinned-photodiodes-4qb0vbc4yy.pdf

Compact Modeling of Charge Transfer in Pinned Photodiodes for CMOS Image Sensors

The charge holding capacity of a pinned photodiode (PPD) in CMOS image sensors (CISs) is determined by the capacitance of the photodiode. A PPD with a higher full-well capacity (FWC) is desirable for a higher dynamic range and image contrast thereby improving the image quality. The dependence of FWC of a PPD on light intensity and integration time is reported in the literature. However, there is no generalized method to estimate the PPD capacitance. The reported models assume the PPD capacitance to be constant and independent of operating conditions. This paper presents an improved model to accurately estimate the dynamic behavior of the PPD capacitance at low and high light intensity levels and varying temperature in CISs. It is observed that the logarithmic increase in light intensity and integration time increases the photodiode capacitance linearly. The model shows good agreement with the simulated and measured values of photodiode capacitance.

Dynamic Capacitance Model of a Pinned Photodiode in CMOS Image Sensors

A new mathematical model is proposed for the capacitance of the pinned photodiode (PPD) taking into account the potential changes at the PPD center. Aside from the electric field and the depletion region that is created by the p-n junctions, a depletion process occurs at the center of PPD. In this letter, the total capacitance of PPD is demonstrated to be composed of two series capacitances; the junction capacitance around the PPD and the inner capacitance at the PPD center. For the junction capacitance calculation, a previously developed model can be utilized. On the other hand, the inner capacitance is a result of the depletion at the PPD center, which is modeled in this letter. Both capacitances are voltage-dependent and the total series capacitance fits to the measurement data.

A New Analytical Pinned Photodiode Capacitance Model

The full well capacity (FWC) of the four-transistor pixel in CMOS image sensors (CISs) should be a constant which is decided by photodiode structure, doping, and manufacturer, whereas the measured FWC in experiments varies with the incident light intensity. In this paper, a model for the light-dependent FWC is developed. The model includes two sources that contribute to the extra light-dependent charge. They are collected along with the intrinsic full well charge in the photodiode or the floating diffusion. The first source comes from the equilibrium between the photocurrent and the photodiode forward current. The other source is the extra collected charges during charge transfer. An analysis model is developed to describe these two light-dependent sources, and the saturated output shows logarithmic and linear relationship with light intensity at low- and high-light condition, respectively. A device level simulation using technology computer aided design software was performed to verify the proposed model. Furthermore, a prototype chip with 15- $\mu \text{m} \times 15$ - $\mu \text{m}$ pixels fabricated in a 0.18- $\mu \text{m}$ CIS process was tested. The simulation and measurement results exhibit fairly good consistency with the proposed model. The estimation of the intrinsic FWC is also discussed.

Analysis and Modeling of the Light-Dependent Full Well Capacity of the 4-T Pixel in CMOS Image Sensors

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ( $\Delta \varphi _{M}$ ) and maximum electron quasi-fermi level potential variation ( $\Delta $ FP $_{M}$ ). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$ . In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$ . The proposed model is verified by two previously reported experiment-based data.

Analytical Modeling of Pinning Process in Pinned Photodiodes

An improved analytical model for quantifying the full well capacity in pinned photodiode (PPD) CMOS image sensors is proposed. The model captures the characteristics of the realistic technology-induced vertical doping nonuniformity in photon sensing N-type area of the PPD structure and the voltage dependency of the PPD capacitance, respectively, both of which were neglected in the existing works. Excellent agreement between measured and predicted data shows that the proposed model fits a wider range of technology conditions for a wider spectra responding compared to the up-to-date reported model.

Benlan Shen

Papers

An Improved Model for the Full Well Capacity in Pinned Photodiode CMOS Image Sensors