A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.

Shallow trench isolation process

A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

Semiconductor devices having strained dual channel layers

In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.

Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry

A new method to form a VLSI-photonic heterogeneous system device is achieved. The method comprises providing an optical substrate comprising at least one passive optical component formed therein. An electronic substrate is provided comprising at least one active electronic component formed therein. A plurality of metal pillars are formed through the optical substrate and protruding out a first surface of the optical substrate. A plurality of metal pads are formed on a first surface of the electronic substrate. The optical substrate and the electronic substrate are bonding together by a method further comprising aligning the first surfaces of the optical and electronic substrates such that the protruding metal pillars contact the metal pads. The optical and electronic substrates are then thermally treated such that the metal pillars bond to the metal pads.

VLSI-photonic heterogeneous integration by wafer bonding

The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector

An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Si/SiGe optoelectronic integrated circuits

PROBLEM TO BE SOLVED: To simply integrate a high-speed and high-response photo detector in a monolithic form, by the method wherein a quantum well layer functions as a conductive channel so that a spacer layer separates a dopant in a supply layer from the conductive channel. SOLUTION: It comprises a single crystal semiconductor substrate 1, Si1-x Gex buffer layer 2 graded from x=0 to y ranging from 0.1 to 1.0, relaxing Si1-x Gex layer 3 of 0.25-10 μm thick, quantum well layer 4, undoped Si1-y Gey spacer layer 5 and doped Si1-y Gey supply layer 6. The relaxing Si1-x Gex layer 3 functions as an absorption region of a photo detector, the quantum well layer 4 can function as a conductive channel of a field effect transistor and the spacer layer 5 functions so as to separate a dopant in the supply layer from the conductive channel. Thus it is possible to manufacture a photo detector having an elevated speed and response, compared with a bulk Si.

Bernd-Ulrich H Klepser

Papers

Si/SiGe optoelectronic integrated circuits

Si/sige photoelectronic integrated circuit and forming method thereof

Si/SiGe optoelektronische integrierte Schaltungen