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Binyong He

Researcher at Changsha University of Science and Technology

Publications -  9
Citations -  230

Binyong He is an academic researcher from Changsha University of Science and Technology. The author has contributed to research in topics: Logic gate & Electronic circuit. The author has an hindex of 5, co-authored 8 publications receiving 135 citations.

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Analysis and FPGA Realization of a Novel 5D Hyperchaotic Four-Wing Memristive System, Active Control Synchronization, and Secure Communication Application

TL;DR: This research demonstrates that the hardware-based design of the 5D HFWMS can be applied to various chaos-based embedded system applications including random number generation, cryptography, and secure communication.
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Design and FPGA Implementation of a Pseudorandom Number Generator Based on a Four-Wing Memristive Hyperchaotic System and Bernoulli Map

TL;DR: In this article, a pseudorandom number generator (PRNG) based on a no-equilibrium four-wing memristive hyperchaotic system (FWMHS) and its implementation on Field Programmable Gate Array (FPGA) board is presented.
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CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua’s Chaotic System with Coexisting Multiple Attractors

TL;DR: This study demonstrates that the hardware-based multistable modified fourth-order autonomous Chua’s chaotic system is a very good source of entropy and can be applied to various embedded systems based on chaos, including secure communication, cryptography, and random number generator.
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Pseudorandom number generator based on a 5D hyperchaotic four-wing memristive system and its FPGA implementation - PRNG based on a 5D hyperchaotic four-wing memristive system and its FPGA implementation

TL;DR: A FPGA PRNG based on a 5D hyperchaotic four-wing memristive system (HFWMS) has multiline equilibrium and three positive Lyapunov exponents, which indicates that the system has very complex dynamic behavior.
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Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

TL;DR: A new approach for analyzing the propagation probabilities of SET in logic circuits by considering three fault masking effects, matrix union operations and SET Propagation Probabilities Matrices is presented.