B
Blair Fort
Researcher at University of Toronto
Publications - 11
Citations - 664
Blair Fort is an academic researcher from University of Toronto. The author has contributed to research in topics: High-level synthesis & Debugging. The author has an hindex of 6, co-authored 11 publications receiving 542 citations.
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Journal ArticleDOI
A Survey and Evaluation of FPGA High-Level Synthesis Tools
Razvan Nane,Vlad-Mihai Sima,Christian Pilato,Jongsok Choi,Blair Fort,Andrew Canis,Yu Ting Chen,Hsuan Hsiao,Stephen J. Brown,Fabrizio Ferrandi,Jason H. Anderson,Koen Bertels +11 more
TL;DR: This work uses a first-published methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources.
Proceedings ArticleDOI
A Multithreaded Soft Processor for SoPC Area Reduction
TL;DR: A multithreaded (MT) soft processor for area reduction in SoPC implementations is presented, which can achieve an area savings of about 45% for the processor itself in addition to the area savings due to not replicating CI logic blocks.
Proceedings ArticleDOI
From software to accelerators with LegUp high-level synthesis
Andrew Canis,Jongsok Choi,Blair Fort,Ruolong Lian,Qijing Huang,Nazanin Calagar,Marcel Gort,Jia Jun Qin,Mark Aldham,Tomasz Czajkowski,Stephen J. Brown,Jason H. Anderson +11 more
TL;DR: This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.
Proceedings ArticleDOI
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis
Blair Fort,Andrew Canis,Jongsok Choi,Nazanin Calagar,Ruolong Lian,Stefan Hadjis,Yu Ting Chen,Mathew Hall,Bain Syrowik,Tomasz Czajkowski,Stephen J. Brown,Jason H. Anderson +11 more
TL;DR: The LegUp framework is overviewed and support for an embedded ARM processor, as is available on Altera's recently released SoC FPGA, HLS support for software parallelization schemes -- pthreads and OpenMP, and a preliminary debugging and verification framework providing C source-level debugging of HLS hardware are described.
Proceedings ArticleDOI
Experiences with soft-core processor design
TL;DR: The UT Nios implementation of Altera's Nios architecture is described and a benchmark set appropriate for soft-core processors is defined.