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Showing papers by "Bobby Brar published in 2004"


Proceedings ArticleDOI
13 Dec 2004
TL;DR: In this paper, a static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.47/As/InP DHBT technology.
Abstract: A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. The divider operation is fully static, operating from f/sub dk/ = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.

26 citations


Proceedings ArticleDOI
01 Jan 2004
TL;DR: In this article, a static frequency dividers with a maximum clock frequency > 110 GHz were designed and fabricated in a narrow mesa InP/In/sub 0.47/As/InP DHBT technology.
Abstract: Static frequency dividers with a maximum clock frequency > 110 GHz were designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. Divider operation is fully static, operating from f/sub clk/ = 4 GHz to 118.70 GHz and dissipating 686.4 mW of power from a -4.2 Volt supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a collector-to-emitter area ratio of 3.0. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies > 100 GHz.

7 citations


Journal ArticleDOI
TL;DR: In this paper, the growth and transport characteristics of stepped InAs/InAs1−xPx quantum wells with AlSb barriers were studied as a function of growth temperature and phosphorus content.
Abstract: We report the growth and transport characteristics of stepped InAs/InAs1−xPx quantum wells with AlSb barriers. Electron mobilities and carrier concentrations in these composite stepped quantum wells were studied as a function of growth temperature and phosphorus content. For InAs1−xPx grown at 430 °C substrate temperature (nominal x=0.2), a high 22 500 cm2/V s electron mobility was observed, while 7100 cm2/V s mobility was observed in a single strained InAs1−xPx quantum well layer. Heterostructure field-effect transistors fabricated using the composite quantum wells exhibited increased breakdown voltage and a 14:1 reduction in source-drain dc conduction when compared to a similar InAs-channel device.

6 citations