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Showing papers by "Bulent Abali published in 2001"


Journal ArticleDOI
TL;DR: Results show that the hardware compression of main memory has a negligible penalty compared to an uncompressed main memory, and for memory-starved applications it increases performance significantly, and the memory content of an application can usually be compressed by a factor of 2.
Abstract: A novel memory subsystem called Memory Expansion Technology (MXT) has been built for fast hardware compression of main-memory content. This allows a memory expansion to present a "real" memory larger than the physically available memory. This paper provides an overview of the memory-compression architecture, its OS support under Linux and Windows®, and an analysis of the performance impact of memory compression. Results show that the hardware compression of main memory has a negligible penalty compared to an uncompressed main memory, and for memory-starved applications it increases performance significantly. We also show that the memory content of an application can usually be compressed by a factor of 2.

106 citations


Proceedings ArticleDOI
Bulent Abali1, Hubertus Franke, Xiaowei Shen, Dan E. Poff, T.B. Smith 
20 Jan 2001
TL;DR: An analysis of the performance impact of memory compression using the SPEC2000 benchmarks and a database benchmark shows that the hardware compression of memory has a negligible performance penalty compared to a standard memory.
Abstract: A new memory subsystem called Memory Expansion Technology (MXT) has been built for compressing main memory contents. MXT effectively doubles the physically available memory. This paper provides an analysis of the performance impact of memory compression using the SPEC2000 benchmarks and a database benchmark. Results show that the hardware compression of memory has a negligible performance penalty compared to a standard memory. We also show that many applications' memory contents can be compressed usually by a factor of two to one. We demonstrate this using industry benchmarks, web server benchmarks, and contents of popular web sites.

79 citations


Journal ArticleDOI
TL;DR: The results indicate that MXT improves price/performance by 25% to 70%.
Abstract: Memory Expansion Technology (MXT™) has been discussed in a number of forums. It is a hardware-implemented means for software-transparent on-the-fly compression of the main-memory content of a computer system. For a very broad set of workloads, it provides a compression ratio of 2:1 or better. This ability to compress and store data in fewer bytes effectively doubles the apparent capacity of memory at minimal cost. While it is clear that a doubling of memory at little cost is bound to improve the price/performance of a system that can be offered to customers, the magnitude of the impact of MXT on price/performance has not been quantified. This paper estimates the range of price/performance improvements for typical workloads from available data. To summarize, the results indicate that MXT improves price/performance by 25% to 70%. The competitive impact of such a large step function in price/performance from a single technology is profound; it is comparable to the entire gross margin in the competitive market for "PC servers."

32 citations


Journal ArticleDOI
Bulent Abali1, Xiaowei Shen1, Hubertus Franke1, Dan E. Poff1, T.B. Smith1 
TL;DR: This paper describes operating system techniques that can deal with dynamically changing memory sizes and shows that the hardware compression of memory has a negligible performance penalty compared to a standard memory for many applications and improves the performance significantly.
Abstract: A new memory subsystem, called Memory Xpansion Technology (MXT), has been built for compressing main memory contents. MXT effectively doubles the physically available memory transparently to the CPUs, input/output devices, device drivers, and application software. An average compression ratio of two or greater has been observed for many applications. Since compressibility of memory contents varies dynamically, the size of the memory managed by the operating system is not fixed. In this paper, we describe operating system techniques that can deal with such dynamically changing memory sizes. We also demonstrate the performance impact of memory compression using the SPEC CPU2000 and SPECweb99 benchmarks. Results show that the hardware compression of memory has a negligible performance penalty compared to a standard memory for many applications. For memory starved applications and benchmarks such as SPECweb99, memory compression improves the performance significantly. Results also show that the memory contents of many applications can be compressed, usually by a factor of two to one.

31 citations


Patent
Aruna V. Ramanan1, Bulent Abali1
19 Nov 2001
TL;DR: Fanning route generation for multi-path networks has been proposed in this article, where a source node-destination node (S-D) group having common starting and ending sets of links from the network of interconnected nodes is selected.
Abstract: A fanning route generation technique is provided for multi-path networks having a shared communications fabric. The technique includes selecting a source node—destination node (S-D) group having common starting and ending sets of links from the network of interconnected nodes. Within this group, selecting the shortest routes between the S-D nodes of the group so that: selected routes substantially uniformly fan out from the source node to a center of the network and fan in from the center of the network to the destination node, thereby achieving local balance; and global balance of routes passing through links that are at a same level of the network is achieved.

25 citations


Journal ArticleDOI
TL;DR: The performance of the implemented VIA surpasses that of other existing software implementations of the VIA and is comparable to that of a hardware VIA implementation.

14 citations


Journal ArticleDOI
TL;DR: The architecture of Switch2 switch chip, the recently developed third generation switching element which future IBM RS/6000 SP systems may be based on, is described and two novel algorithms for generating adaptive routes specifications required for enabling the usage of adaptive source routing are proposed.

4 citations