Bulent Abali

TL;DR: In this paper, the authors present a memory compression operation and a method to manage memory levels in a processor by initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level.

TL;DR: In this paper, the Huffman code is implemented in a holding register where a main data input and a lookahead input are held in a hold register, and a plurality of half-decoders decode, in parallel, in a single clock cycle, a subset of frequently-occurring code words of a Huffman Code.

TL;DR: In this article, a set of disks in a plurality of disk arrays are configured to have one or more spare partitions, and a service visit is scheduled for replacement of the failed disks.

TL;DR: In this article, the authors propose an LZB algorithm to reduce the number of writes to the main memory to increase the useful life of main memory, where data to be written is written to a cache line in a lowestlevel cache memory and in a higher level cache memory(s).

TL;DR: In this article, the coprocessor engine is suspended from performing operations for a first client so that it may begin operating for a second client while saving metadata about its operation state at the time of the suspend.