This paper reviews progress in SiGe Heterojunction Bipolar Transistors (HBT) on Silicon-On-Insulator (SOI) technology. SiGe HBTs on SOI are attractive for mixed signal radio frequency (RF) applications and have been of increasing research interest due to their compatibility with SOI CMOS (Complementary Metal Oxide Semiconductor) technology. In bipolar technology, the use of SOI substrate eliminates parasitic substrate transistors and associated latch-up, and has the ability to reduce crosstalk, particularly when combined with buried groundplanes (GP). Various technological SOI bipolar concepts are reviewed with special emphasis on the state-of-the-art SOI SiGe HBT devices in vertical and lateral design. More in depth results are shown from a UK consortium advanced RF platform technology, which includes SOI SiGe HBTs. Bonded wafer technology was developed to allow incorporation of buried silicide layers both above and below the buried oxide. New electrical and noise characterisation results pointed to reduced 1/f noise in these devices compared to bulk counterparts. The lower noise is purported to arise from strain relief of the device structure due to the elasticity of the buried oxide layer during the high temperature epitaxial layer growth. The novel concept of the silicide SOI (SSOI) SiGe HBT technology developed for targeting a reduction in collector resistance, as well as for suppressing the crosstalk, is outlined. The buried tungsten silicide layers were found to have negligible impact on junction leakage. Further to vertical SiGe HBTs on SOI, the challenges of fabricating a lateral SOI SiGe HBT structure are presented.

Review of SiGe HBTs on SOI

Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a source and a drain of the CMOS are formed of SiGe and metal, and thus leakage current is prevented and low power consumption is achieved. Also, heat generation in a chip is suppressed, and a wide operation range may be obtained even at a low voltage.

NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same

We propose and simulate a new device combining a tunneling field-effect transistor (TFET) with a heterojunction bipolar transistor (HBT). The carriers generated in the tunneling junction are used as base current to drive the HBT and obtain a high bipolar current. Owing to the sharp switching of the TFET and high HBT current gain, the CMOS-compatible Si/Si1-xGex device shows a subthreshold swing of <; 60 mV/ dec over seven decades of current, a high ON current, and scaling capability down to 10 nm.

Novel Bipolar-Enhanced Tunneling FET With Simulated High On-Current

High-sensitivity Si-based backward diodes were realized that are monolithically integratable with transistor circuitry. Potential applications include large area focal plane arrays. The Si-based backward diodes exhibit a high zero-biased curvature coefficient, /spl gamma/, of 31 V/sup -1/ and a low zero biased junction capacitance, C/sub j/, of 9 fF//spl mu/m/sup 2/, all at room temperature. The predicted low frequency voltage sensitivity, /spl beta//sub V/, for a 50 /spl Omega/ source is 3100 V/W. The high sensitivity, low junction capacitance, and Si/SiGe heterojunction bipolar transistor compatibility of the Si-based backward diodes make them very attractive for zero-bias square-law detector applications.

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High sensitivity Si-based backward diodes for zero-biased square-law detection and the effect of post-growth annealing on performance

Provided are bipolar transistor, BiCMOS device and method of fabricating thereof, in which an existing sub-collector disposed beneath a collector of a SiGe HBT is removed and a collector plug disposed at a lateral side of the collector is approached to a base when fabricating a Si-based very high-speed device, whereby it is possible to fabricate the SiGe HBT and an SOI CMOS on a single substrate, reduce the size of the device and the number of masks to be used, and implement the device of high density, low power consumption, and wideband performance

Bipolar transistor, BiCMOS device, and method for fabricating thereof

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.

Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

We demonstrate multi-emitter Si/Ge/sub x/Si/sub 1-x/ n-p-n heterojunction bipolar transistors (HBT's) which require no base contact for transistor operation. The base current is supplied by the additional emitter contact under reverse bias due to the heavy doping of the emitter-base junction. Large-area HBT test structures exhibit good transistor characteristics, with current gain /spl beta//spl ap/400 regardless of whether the base current is supplied by a test base electrode or one of the emitter contacts. These devices have enhanced logic functionality because of emitter contact symmetry. Since device fabrication does not require base electrode formation, the number of processing steps can be reduced without significant penalty to HBT performance.

Multi-emitter Si/Ge x Si/sub 1-x/ heterojunction bipolar transistor with no base contact and enhanced logic functionality

We demonstrate multi-emitter Si/Ge Si npn het- erojunction bipolar transistors (HBT's) which require no base contact for transistor operation. The base current is supplied by the additional emitter contact under reverse bias due to the heavy doping of the emitter-base junction. Large-area HBT test structures exhibit good transistor characteristics, with current gain regardless of whether the base current is supplied by a test base electrode or one of the emitter contacts. These devices have enhanced logic functionality because of emitter contact symmetry. Since device fabrication does not require base electrode formation, the number of processing steps can be reduced without significant penalty to HBT performance.

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Multi-emitter Si/Ge Si Heterojunction Bipolar Transistor with No Base Contact and Enhanced Logic Functionality

Previously we demonstrated a new class of VLSI-compatible multiemitter Si/SiGe/Si npn HBTs with enhanced logic functionality. These devices have two (or more) emitter contacts and no base contact. Given a potential difference between any two emitter contacts, one of the emitter-base junctions is forward biased and injects electrons into the base, while the other junction is reverse biased and small controlling current flows by interband tunneling. Because of emitter contact symmetry, the device possesses exclusive or functionality. Our first devices provided current gain of ~400 at room temperature, at an operating voltage of ~2 V. Here we present an improved version that operates at 1 V, as well as a multiemitter HBT fabrication sequence that is not only fully compatible with a VLSI BiCMOS process, but even saves several processing steps comapred to a standard HBT.

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C. A. King

Papers

Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

Multi-emitter Si/Ge x Si/sub 1-x/ heterojunction bipolar transistor with no base contact and enhanced logic functionality

Multi-emitter Si/Ge Si Heterojunction Bipolar Transistor with No Base Contact and Enhanced Logic Functionality

VLSI-COMPATIBLE PROCESSING AND LOW-VOLTAGE OPERATION OF MULTIEMITTER Si/SiGe HETEROJUNCTION BIPOLAR TRANSISTORS