An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Avalanche photodiodes, which operate above the breakdown voltage in Geiger mode connected with avalanche-quenching circuits, can be used to detect single photons and are therefore called singlephoton avalanche diodes SPAD's. Circuit configurations suitable for this operation mode are critically analyzed and their relative merits in photon counting and timing applications are assessed. Simple passive-quenching circuits (PQC's), which are useful for SPAD device testing and selection, have fairly limited application. Suitably designed active-quenching circuits (AQC's) make it possible to exploit the best performance of SPAD's. Thick silicon SPAD's that operate at high voltages (250-450 V) have photon detection efficiency higher than 50% from 540- to 850-nm wavelength and still ~3% at 1064 nm. Thin silicon SPAD's that operate at low voltages (10-50 V) have 45% efficiency at 500 nm, declining to 10% at 830 nm and to as little as 0.1% at 1064 nm. The time resolution achieved in photon timing is 20 ps FWHM with thin SPAD's; it ranges from 350 to 150 ps FWHM with thick SPAD's. The achieved minimum counting dead time and maximum counting rate are 40 ns and 10 Mcps with thick silicon SPAD's, 10 ns and 40 Mcps with thin SPAD's. Germanium and III-V compound semiconductor SPAD's extend the range of photon-counting techniques in the near-infrared region to at least 1600-nm wavelength.

Avalanche photodiodes and quenching circuits for single-photon detection

Music is blanket transmitted (for example, via satellite downlink transmission) to each customer's computer-based user station. Customers preselect from a list of available music in advance using an interactive screen selector, and pay only for music that they choose to have recorded for unlimited playback, for example, by a “CD burner”. An antipiracy “ID tag” is woven into the recorded music so that any illegal copies therefrom may be traced to the purchase transaction. Music is transmitted on a fixed schedule or through an active scheduling process that monitors music requests from all or a subset of satellite receivers and adjust scheduling according to demand for various CD's. Receivers store selections that are likely to be preferred by a specific customer. In those instances where weather conditions, motion atmospheric layers or dish obstructions result in data loss, the system downloads the next transmission of the requested CD and uses both transmissions to produce a “good copy”. In conjunction with the blanket transmission of more popular music, an automated CD manufacturing facility may be provided to manufacture CD's that are not frequently requested and distribute them by ground transportation.

Music distribution systems

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

This work presents recent results on Secondary Electron flash memory, and contrasts this approach to standard for scaled, low power mass storage applications.

Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below

In this paper, we present a comprehensive experimental characterization of electron and hole effective mobility (/spl mu//sub eff/) of ultrathin SOI n- and p-MOSFETs. Measurements have been performed at different temperatures using a special test structure able to circumvent parasitic resistance effects. Our results indicate that, at large inversion densities (N/sub inv/), the mobility of ultrathin SOI transistors is largely insensitive to silicon thickness (T/sub SI/) and is larger than in heavily doped bulk MOS because of a lower effective field. At small N/sub inv/, instead, mobility of SOI transistors exhibits a systematic reduction with decreasing T/sub SI/. The possible explanation for this /spl mu//sub eff/ degradation in extremely thin silicon layers is discussed by means of a comparison to previously published experimental data and theoretical calculations. Our analysis suggests a significant role is played by an enhancement of phonon scattering due to carrier confinement in the thinnest semiconductor films. The experimental mobility data have then been used to study the possible implications for ultrashort SOI transistor performance using numerical simulations.

Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application

In this paper, we report an experimental investigation of electron mobility in ultrathin SOI MOSFETs operated in double-gate mode. Mobility is measured for silicon thickness down to approximately 5 nm and for different temperatures. Mobility data in single- and double-gate mode are then compared according to two different criteria imposing either the same total inversion charge density or the same effective field in the two operating modes. Our results demonstrate that for silicon films around 10 nm or thinner and at small inversion densities, a modest but unambiguous mobility improvement for double-gate mode operation is observed even if the same effective field as in the single-gate mode is kept. Furthermore, we also document that the mobility in double-gate mode can improve markedly above single-gate mobility when the comparison is made at the same total inversion density. This latter feature of the double-gate operating mode can be very beneficial in the perspective of very-low voltage operation.

An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

Electron and hole effective mobilities of ultra-thin SOI N- and P-MOSFETs have been measured at different temperatures using a special test structure able to circumvent parasitic resistance effects. At large inversion densities (N/sub inv/) ultra-thin SOI mobility can be higher than in heavily doped bulk MOS due a lower effective field and it is largely insensitive to silicon thickness (T/sub SI/). However, at small Ni/sub inv/ the mobility is clearly reduced for decreasing T/sub SI/. The effective mobility data are used to study the implications for ultra-short MOS transistor performance at device simulation level.

Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs

We have investigated for the first time the propagation of the avalanche multiplication over the area of p‐n junctions reverse biased above the breakdown voltage. The multiplication process spreads from the point where the avalanche is triggered to the whole junction area with a speed proportional to the final steady‐state value of the avalanche current. The values of the propagation speed suggest that the phenomenon is due to diffusion of carriers assisted by avalanche multiplication. This effect strongly affects the rise of the avalanche current and turns out to limit the performance of single photon avalanche diodes.

Marco Mastrapasqua

Papers

Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below

Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application

An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs

Observation of avalanche propagation by multiplication assisted diffusion in p-n junctions