Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Basic mechanisms and modeling of single-event upset in digital microelectronics

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

Developments in the field of destructive single-event effects over the last 40 years are reviewed. Single-event latchup, single-event burnout, single-event gate rupture, and single-event snap-back are discussed beginning with the first observation of each effect, its phenomenology, and the development of present day understanding of the mechanisms involved.

Destructive single-event effects in semiconductor devices and ICs

Large-scale three-dimensional (3D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3D simulations show excellent agreement with broadbeam cross section curves and microbeam, charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

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SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors. These errors are random and not related to permanent hardware faults. Their causes may be internal (e.g., interconnect coupling) or external (e.g., cosmic radiation). To meet the system reliability requirements it is necessary for both the circuit designers and test engineers to get the basic knowledge of the soft errors. We present a tutorial study of the radiation-induced single event upset phenomenon caused by external radiation, which is a major source of soft errors. We summarize basic radiation mechanisms and the resulting soft errors in silicon. Soft error mitigation techniques with time and space redundancy are illustrated. An industrial design example, the IBM z990 system, shows how the industry is dealing with soft errors these days.

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Single Event Upset: An Embedded Tutorial

For particular bias conditions, it is shown that a device can fail due to either single-event gate rupture (SEGR) or to single-event burnout (SEB). The likelihood of triggering SEGR is shown to be dependent on the ion impact position. Hardening techniques are suggested.

SEGR and SEB in n-channel power MOSFETs

This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.

SEU critical charge and sensitive area in a submicron CMOS technology

Triggering of Single Event Burnout (SEB) in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is studied by means of experiments and simulations based on real structures. Conditions for destructive and nondestructive events are investigated through current duration observations. The effect of the ion's impact position is experimentally pointed out. Finally, further investigation with 2D MEDICI simulations show that the different regions of the MOSFET cell indeed exhibit different sensitivity with respect to burnout triggering. >

Evidence of the ion's impact position effect on SEB in N-channel power MOSFETs

The use of the 2D simulator MEDICI as a tool for single event burnout (SEB) comprehension is investigated. Simulation results are compared to experimental currents induced in an N channel power MOSFET by the ions from a /sup 252/Cf source. Current measurements have been carried out using a specially designed circuit. Simulations make it possible to analyze separately the effects of the ion impact and the electrical environment parameters on the SEB phenomenon. Burnout sensitivity is found to be increased by increasing supply voltage and ion linear energy transfer (LET), and by decreasing load charge. These electrical tendencies are confirmed by experiments. Burnout sensitivity is also found to be sensitive to the ion impact position. The current shape variations for given electrical parameters can be related to LET or ion impact position changes. However, some experimental current shapes are not reproduced by simulations. >

Experimental and 2D simulation study of the single-event burnout in N-channel power MOSFETs

2D MEDICI simulator is used to investigate hardening solutions to single-event burnout (SEE). SEE parametric dependencies such as carrier lifetime reduction, base enlargement, and emitter doping decrease have been verified and a p/sup +/ plug modification approach for SEE hardening of power MOSFETs is validated with simulations on actual device structures.

C. Dachs

Papers

SEGR and SEB in n-channel power MOSFETs

SEU critical charge and sensitive area in a submicron CMOS technology

Evidence of the ion's impact position effect on SEB in N-channel power MOSFETs

Experimental and 2D simulation study of the single-event burnout in N-channel power MOSFETs

Simulation aided hardening of N-channel power MOSFETs to prevent single event burnout