In this paper, a strategy for the design of source-coupled logic (SCL) gates both with and without an output buffer is proposed. Closed-form design equations to size bias currents and transistor aspect ratios to meet assigned specifications are derived from a simple SCL gate analytical delay model, shown to be sufficiently accurate by extensive simulations. The design criteria proposed are simple and provide the designer with a more profound understanding of the tradeoff between delay and power consumption. More specifically, design criteria are derived to consciously manage this tradeoff in practical design cases, i.e., when either high performance or an optimum balance with power dissipation is needed. Therefore, the strategy proposed is useful right from the early design phases, and avoids tedious simulation iterations.

Design strategies for source coupled logic gates

This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

Positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits Positive feedback allows for significantly reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters Spectre simulations by using a 035-/spl mu/m CMOS process confirm that the proposed models are sufficiently accurate in practical cases PFSCL gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4 The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation

Modeling and evaluation of positive-feedback source-coupled logic

Switching noise due to di/dt is becoming severe as technology states, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per V/sub DD/ and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5/spl times/ and VDD/GND line bounce by 1.7/spl times/ and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer.

Low switching noise and load-adaptive output buffer design techniques

Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells

This paper presents a design procedure of a high-frequency output driver with low power-bus noise and with an architecture which automatically adapts to different loading. In depth analysis of a noise amplitude versus driving power as a first stage of design is included and the theoretical approach is supported by simulation and measurement results of a designed and manufactured device.

Design procedure of low-noise high-speed adaptive output drivers

This article is an asynchronous approach to bit-serial processing. A new asynchronous cell (DCVSL like) was designed containing simplified "complete" signal generation as part of a dynamic handshake circuitry. The problem of data feedback has been addressed and its solution in a modified handshake protocol and local memory inclusion is given. Basic arithmetic components are demonstrated and a larger system is used as an example of this new cost effective technique.

Asynchronous logic in bit-serial arithmetic

In this paper new findings to design fast and low noise generating CMOS output drivers are presented. The adaptive technique applied not only reduces power-rail noise, but also removes overshoots and unnecessary switching. A new multistage output driver is compared to four standard designs for time delay, maximum dynamic current and power-rail noise under various loading conditions. A comparison of silicon area is also given.

C.F. Chan

Papers

Design procedure of low-noise high-speed adaptive output drivers

Asynchronous logic in bit-serial arithmetic

On design of low-noise adaptive output drivers