This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

Register transfer level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking technology and progressive increase in clock frequency are bringing clock to its physical limits. Asynchronous circuits, which are believed to replace globally clocked designs in the future, remain out of the competition due to the design complexity of some automated approaches and poor results of other techniques. Successful asynchronous designs are known but they are primarily custom. This work sketches an automated approach for automatically re-implementing conventional RTL designs as fine-grain pipelined asynchronous quasi-delay-insensitive (QDI) circuits and presents a framework for automated synthesis of such implementations from high-level behavior specifications. Experimental results are presented using our new dynamic asynchronous library.

An automated fine-grain pipelining using domino style asynchronous library

In this paper, a design of a 16-bit asynchronous multiplier is presented. The multiplier core consists of small basic blocks. Each block includes handshake and computation logic and communicates with four neighbor cells in asynchronous handshake fashion using four-phase protocol. The computation logic is implemented in dual-rail coded domino logic. The input and output signals of the multiplier are single-rail coded. The single-rail coding allows communication with other single-rail coded asynchronous blocks using four-phase signaling. The design speed is self-adjusting to the technology parameters and supply voltage variations. The multiplier has low latency and achieves a throughput rate of 250 MHz. The multiplier was fabricated in a 0.6-/spl mu/m CMOS process and has a core size of 4.3/spl times/2.1 mm.

Asynchronous cross-pipelined multiplier

In most of the multimedia applications such as audio, speech, graphics and video the final output is interpreted by human senses, which are insensitive to small errors. So, it is not required to produce exact numerical outputs. Considering the advantage of relaxation in numerical accuracy, this paper propose several approximate multipliers for error tolerant applications which are designed by using approximate adders. Approximate adder is constructed by reducing the complexity at the transistor level. The power consumption is reduced due to decrease in number of transistors and switched capacitance. Decrease in the number of series connected transistors, lead to shorter critical paths. Propagation delay is appreciably reduced due to decrease in load capacitance. The operation of 4×4, 8×8 and 16×16 approximate array multipliers are discussed in this paper. Simulation results show that for random inputs, upto 64% savings in power delay product is achieved using the proposed multiplier, when compared with the conventional multiplier.

Low power, high speed error tolerant multiplier using approximate adders

Nowadays, there are many Cryptographic Applications that demand both high speed and low power. In order to meet this requirement, we have designed a new asynchronous Data Encryption Standard (DES) data encryption chip and decided that can be used in contactless smart cards. There are many advantages to use Asynchronous Circuit Design in smart card chips, such as low power consumption and no global clock. We will use a 0.6 /spl mu/m CMOS technology to fabricate the chip and the RF test circuit.

A low power asynchronous DES

In this paper we present a new handshake cell, which is used to construct a pipeline called Locally Distributed Asynchronous pipeline (LDA). The handshakes generate control signals, which form 4-phase signaling communication protocol. A 64-bit parity encoder designed using the LDA pipeline has shown to be faster than other asynchronous/synchronous implementations of the encoder.

https://ieeexplore.ieee.org/iel5/7722/21171/00982621.pdf

A fine-grain asynchronous pipeline reaching the synchronous speed

This article is an asynchronous approach to bit-serial processing. A new asynchronous cell (DCVSL like) was designed containing simplified "complete" signal generation as part of a dynamic handshake circuitry. The problem of data feedback has been addressed and its solution in a modified handshake protocol and local memory inclusion is given. Basic arithmetic components are demonstrated and a larger system is used as an example of this new cost effective technique.

J. Povazanec

Papers

Asynchronous cross-pipelined multiplier

A fine-grain asynchronous pipeline reaching the synchronous speed

Asynchronous logic in bit-serial arithmetic