Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

A tutorial introduction to research on analog and mixed-signal circuit testing

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

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Defect tolerance in VLSI circuits: techniques and yield analysis

A system and method for predicting yield of integrated circuits includes a characterization vehicle (12) having at least one feature representative of at least one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle. The characterization vehicle (12) is subjected to process operations making up the fabrication cycle to be used in fabricating the integrated circuit in order to produce a yield model (16). The yield model (16) embodies a layout as defined by the characterization vehicle (12) and preferably includes features which facilitates the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine (18) extracts predetermined layout attributes (26) from a proposed product layout (20). Operating on the yield model, the extraction engine (18) produces yield predictions (22) as a function of layout attributes (26) and broken down by layers or steps in the fabrication process (14).

System and method for product yield prediction using device and process neighborhood characterization vehicle

Uncertainties have become a major concern in integrated circuit design. In order to avoid the huge number of repeated simulations in conventional Monte Carlo flows, this paper presents an intrusive spectral simulator for statistical circuit analysis. Our simulator employs the recently developed generalized polynomial chaos expansion to perform uncertainty quantification of nonlinear transistor circuits with both Gaussian and non-Gaussian random parameters. We modify the nonintrusive stochastic collocation (SC) method and develop an intrusive variant called stochastic testing (ST) method. Compared with the popular intrusive stochastic Galerkin (SG) method, the coupled deterministic equations resulting from our proposed ST method can be solved in a decoupled manner at each time point. At the same time, ST requires fewer samples and allows more flexible time step size controls than directly using a nonintrusive SC solver. These two properties make ST more efficient than SG and than existing SC methods, and more suitable for time-domain circuit simulation. Simulation results of several digital, analog and RF circuits are reported. Since our algorithm is based on generic mathematical models, the proposed ST algorithm can be applied to many other engineering problems.

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Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos

In the fast-paced semiconductor industry, time to market means everything. Accommodating the shortened design cycles, however, is hampered by the ever-increasing design complexity. In addition, the continual drive to achieve higher performance (speed, area, power) has fueled the introduction of new manufacturing processes. Existing integrated circuit design methodologies, such as standard-cells designs are failing to cope with these conflicting requirements at a cost that is supported by ASIC product volumes. This report introduces a new regular logic fabric, Via Programmable Gate Arrays (VPGAs). By employing a regular structure, the design cycles can be greatly reduced. Moreover, as the technology dimensions continue scaling downward, the product yield at the ramp-up becomes a function of systematic faults. In order to meet the market demands, the new designs will have to focus on the Manufacturability in addition to the performance specifications. This report presents an overview and design corrections for the common failure mechanisms in modem Cu Integrated Circuit processes. Furthermore, an implementation of the CLB with a manufacturability focus is described.

Design for Manufacturability in Via Programmable Gate Arrays

Integrated circuit manufacturing yields are not necessarily a function of chip area. Accurate yield analysis shows how the yield depends on circuit design and layout. By determining the probabilities of failure and critical areas for different defect types, it is possible to control and manage the yield of integrated circuits. This includes the manufacture of DRAM's, SRAM's, CMOS logic, ASIC's, and CMOS and biCMOS microprocessors. Examples explain the method of meeting yield objectives by setting targets for yield components. In addition, the yield management approach allows for a systematic allocation of resources. Required defect-density learning determines the contamination levels for clean rooms and process equipment. >

C.H. Stapper

Papers

Integrated circuit yield management and yield analysis: development and implementation