IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profile are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.

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Full chip leakage-estimation considering power supply and temperature variations

Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98% accuracy against HSPICE estimates. When applied to interconnection networks, combined with previous proposed dynamic power models, we gain valuable insights on total network power consumption. Our modeling shows router buffers to be a prime candidate for leakage power optimization. We thus investigate the design space of power-aware buffer policies, propose a suite of policies, and explore the impact of various circuits mechanisms on these policies . Simulations show power-aware buffers saving up to 96.6% of total buffer leakage power.

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Leakage power modeling and optimization in interconnection networks

Big data applications have become increasingly popular with the appearance of cloud computing and green computing. Therefore, internet service providers (ISPs) need to build data centers for data storage and data processing under the cloud service pattern. However, data centers often consume a significant amount of energy and lead to pollutant emissions. In recent years, the high energy consumption and environmental pollution of data centers have become a pressing issue. This paper reviews the progress of energy-saving technologies in high-performance computing, energy conservation technologies for computer rooms and renewable energy applications during the construction and operation of data centers. From multiple perspectives of energy consumption, cost reduction, and environment protection, a comprehensive set of strategies are proposed to maximize data centers’ efficiency and minimize the environmental impact. This paper also provides energy-saving trends for data centers in the future.

Optimizing energy consumption for data centers

While there have been several studies and proposals for energy conservation for CPUs and peripherals, energy optimization techniques for selective operating mode control of DRAMs have not been fully explored. It has been shown that as much as 90% of overall system energy (excluding I/O) is consumed by the DRAM modules, serving as a good candidate for energy optimizations. Further; DRAM technology has also matured to provide several low energy operating modes (power modes), making it an opportunistic moment to conduct studies exploring the potential benefits of mode control techniques. This paper conducts an in-depth investigation of software and hardware techniques to avail of the DRAM mode control capabilities at a module granularity for energy savings.

DRAM energy management using software and hardware directed power mode control

With today's design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practice-oriented and suitable for use in an industrial flow.

At-speed transition fault testing with low speed scan enable

Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require consideration of static power in early phases of design development. Design houses that use RTL synthesis based flow for designing ASICs require a quick and reasonably accurate estimate of static power dissipation. This is important for making early packaging decisions and planning the power grid. Keeping this in view, we propose a simple model which enables estimation of static power early in the design phase. Our model is based on the experimental data obtained from simulations at the design level: ln P/sub leak//sup lib/=S/sup lib/ ln Cells+C/sup lib/, where S/sup lib/ and C/sup lib/ are the technology-dependent slope and intercept parameters of the model and "Cells" is the number of cells in the design. The model is validated for a large benchmark circuit and the leakage power predicted by our model is within 2% of the actual leakage power predicted by a popular tool used in the industry.

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Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment

Excessive dynamic voltage drop in the power supply rails during test mode is known to result in false failures and impact yield when testing devices that use low-cost wire-bond packages. Identifying and debugging such test failures is a complex and effort-intensive process, especially when scan compression is involved. From a design cycle-tune view point, it is best to avoid this problem by generating "power-safe" scan patterns. The generation of power-safe patterns must take into consideration the DFT architecture, physical design, tuning and power constraints. In this paper, the authors propose such a framework and show experimental results on some benchmark circuits. The framework can address a non-uniform power grid and region-based power constraints. The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power. The framework includes a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

At-speed testing is becoming crucial for modern very-large-scale-integration systems, which operate at clock speeds of hundreds of megahertz. In a scan-based test methodology, it is common to use a transition delay fault model for at-speed testing. The launching of the transition can be done either in the last cycle of scan shift [launch-off-shift (LOS)], or in a functional launch cycle that follows the scan shift and precedes the fast capture [launch-off-capture (LOC)]. The LOS technique offers significant advantages over the LOC in terms of coverage and pattern count, but since it requires the scan enable (SEN) signal to change state in the time period of one functional clock cycle, considerable engineering resources are required to close the timing on the SEN signal. Low-cost testers will not be able to provide the at-speed SEN signal as required by the LOS technique. We propose a scan-based at-speed methodology that generates "local" SEN signals that are guaranteed to switch in one functional clock cycle even when the external SEN signal does not change state at functional speed. Our technique is based on encapsulating the SEN control signal in the scan test data. A new scan cell, which is called the last transition generator, must be inserted in every scan chain for generating internal SEN signals. The proposed method is robust, practical, and readily implemented using commercial tools available today

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing of these low-cost, low-power devices is a daunting task. Depending on the target application, there are stringent guidelines on the number of defective parts per million shipped devices. At the same time, since such devices are cost-sensitive, test cost is a major consideration. Since system-level power-management techniques are employed in these devices, test generation must be power- management-aware to avoid stressing the power distribution infrastructure in the test mode. Structural test techniques such as scan test, with or without compression, can result in excessive heat dissipation during testing and damage the package. False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss. This paper considers different aspects of testing low-power devices and some new techniques to address these problems.

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C.P. Ravikumar

Papers

At-speed transition fault testing with low speed scan enable

Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

Test strategies for low power devices