We have developed a single/double layer model to explain horizontal shifting of measured D-E hysteresis loops (imprint) for ferroelectric thin films. Such phenomenon can be explained by considering three mechanisms or their multiple effects: (1) stress induced by film/electrode lattice mismatch or clamping, (2) domain pinning induced by, e.g., oxygen vacancies, or (3) degradation of ferroelectric properties in film/electrode surface layers. First, it is found that hysteresis loops under the influence of stress exhibit large horizontal shifts with magnitudes comparable to those observed in experiments. Second, a pseudo-non-switching layer with a large coercive field is assumed to be present at the film/electrode interface in an otherwise homogeneous ferroelectric thin film, and in this case our simulation also shows a large imprint effect. Third, it is also found that time-dependent space-charge-limited conduction is likely to be one origin for the occurrence of imprint.

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Mechanisms of imprint effect on ferroelectric thin films

The effect of Eu substitution on the ferroelectric properties of Bi4Ti3O12 thin films prepared by metal–organic decomposition

Imprint is a degradation mechanism in ferroelectrics that results in the displacement of the polarization hysteresis loop along the electric field axis. We develop a model using a nonlinear thermodynamic analysis coupled with electrostatics to show that such internal voltage offsets can originate from asymmetrically distributed trapped space charges. The electrostatic interactions are established through a built-in polarization due to the space charges and the spontaneous polarization. Numerical results for Ba0.8Sr0.2TiO3 show that the maximum electric field offset does not necessarily occur due to charges trapped near the electrodes.

Imprint in ferroelectric materials due to space charges: A theoretical analysis

The switching current profiles of ferroelectric Pt/Pb(Zr0.4Ti0.6)O3/Pt capacitors were investigated after high-temperature baking to elucidate the mechanisms for retention loss. In the same-state retention, a decrease in the peak value of switching current and increase in the switching time were observed. These changes in the switching characteristics were attributed to the growth of an internal field. By comparing with the switching characteristics of a virgin capacitor and using the Merz equations, we estimated quantitatively the magnitude of the internal field. In the opposite-state retention, backswitching of polarization, triggered by the internal field, was found to be the main cause of the retention loss.

Mechanisms for retention loss in ferroelectric Pt/Pb(Zr0.4Ti0.6)O3/Pt capacitors

Non-volatile FeRAMs based on thin film ferroelectric capacitors are emerging as an advantageous replacement for EEPROM and flash devices. In this work, ferroelectric Al/PbZr x Ti 1− x O 3 (PZT)/SrRuO 3 thin film capacitors were fabricated and its suitability for memory applications was tested. The PZT films, as well as the SrRuO 3 bottom electrodes have been grown by pulsed laser deposition on LaAlO 3 (0 0 1) substrates. Epitaxial heterostructures with high crystalline quality were obtained. Top aluminum electrodes were thermally evaporated onto the PZT films. High dielectric constant of 700 and dielectric loss tangent of 0.03 were obtained. Good ferroelectric behavior with an activation field for switching γ =308 kV/cm and a low coercive voltage of 1.1 V at 40 Hz was observed. The reliability of the thin film capacitors has been tested by means of pulse switching measurements. The polarization shows very little fatigue with cumulative switching. Built-in imprint, arising from the use of asymmetric electrodes, along with induced imprint related to charge trapping at the interfaces were observed.

Growth and characterization of epitaxial ferroelectric PbZrxTi1−xO3 thin film capacitors with SrRuO3 electrodes for non-volatile memory applications

Epitaxial Bi4Ti3O12 (BTO) thin films were deposited on MgO(001) substrates using Pt layers as top and bottom electrodes. In spite of the apparently symmetric capacitor structure, polarization–voltage measurements revealed strong imprint failures and current–voltage measurements showed rectifying behaviors. Imprint pulse tests with a 5 V dc bias and post-annealing treatments suggested that the asymmetric behaviors should be due to interfacial states induced by thermal processes. To probe the interfacial states, capacitance–voltage (C–V) measurements were performed. By fitting the C–V data with a model which describes the Pt/BTO/Pt structure as a series circuit composed of three capacitors, built-in voltages at the top and the bottom interfaces could be determined. Difference in the built-in voltages could explain the imprint failures and the rectifying behaviors. The interfacial states in the BTO capacitors were controlled by varying electrode materials.

C. R. Moon

Papers

Imprint failures and asymmetric electrical properties induced by thermal processes in epitaxial Bi4Ti3O12 thin films