In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we explore methods of reducing energy consumption that do not lead to performance loss (i.e. wasted energy), and explore methods to reduce delay by exploiting instruction level parallelism. We found that careful design reduced the energy dissipation by almost 25%. Pipelining can give approximately a 2/spl times/ improvement in energy-delay product. Superscalar issue, however, does not improve the energy-delay product any further since the overhead required offsets the gains in performance. Further improvements will be hard to come by since a large fraction of the energy (50-80%) is dissipated in the clock network and the on-chip memories. Thus, the efficiency of processors will depend more on the technology being used and the algorithm chosen by the programmer than the micro-architecture.

Energy dissipation in general purpose microprocessors

A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

Content addressable memory device

A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately. Results of properly executed instructions are then committed to architectural state in program order. In this manner, the invention reduces the performance penalty related to mispredictions.

Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction

Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area. >

Saving power by synthesizing gated clocks for sequential circuits

The present invention minimizes unneeded memory accesses by providing a digital processor having control circuit for terminating on-going memory accesses, and by a data transfer circuit that allow jump instructions to be detected sooner in the decode unit. The digital processor includes a decode unit, fetch unit and a memory controller. When the decode unit of the present invention processor determines that a discontinuity must occur in the instruction fetch sequence, it asserts a "jump taken" signal to the fetch unit to indicate that any pre-fetched instruction codes are to be discarded and that fetching is to resume at a new fetch program counter (FPC) value. If the fetch unit is currently stalled because of an outstanding request to the memory controller unit, then the fetch unit asserts an "abort" signal to the memory controller. The memory controller unit interprets the abort signal to mean that the current memory access activity is to be terminated as soon as possible, such that aborting the current operation does not corrupt the stored content of the memory element. In addition to the abort signal, the memory controller unit may assert A "partial-done" signal that informs the fetch unit that some fraction of the current request has been completed. The size of the fractional data made available to the fetch unit will correspond to some size or alignment criteria such that the fetch unit may then be able to forward one instruction code to the decode unit. If the forwarded instruction is a "taken" jump, then the decode unit will be able to abort the current fetch request sooner than if it had to wait for the full request to be satisfied.

Apparatus and method for aborting un-needed instruction fetches in a digital microprocessor device

Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.

Content addressable memory circuitry and method of operation

A method and system within a processor are disclosed for executing selected instructions among a number of instructions stored within a memory, wherein the processor has a maximum of instructions that can dispatched for execution during each processor cycle A subset of the instructions are fetched from the memory for execution A determination is then made whether the set of instructions includes an unresolved branch instruction In response to a determination that the set of instructions includes an unresolved branch instruction, a prediction is made whether a branch indicated by the branch instruction will be taken or will not be taken In response to a prediction that the branch will be taken, a nonsequential target instruction indicated by the branch instruction is fetched from memory A determination is made whether the maximum number of instructions can be dispatched for execution during a processor cycle subsequent to the branch prediction without dispatching instructions within the sequential execution path In response to a determination that less than the maximum number of target instructions can be dispatched in the processor cycle subsequent to the branch prediction without dispatching instructions within the sequential execution path, an instruction within the sequential execution path is speculatively dispatched for execution In response to refutation of the branch prediction, the fetch of the nonsequential target instruction is cancelled and the instruction within the sequential execution path is executed, thereby minimizing a performance penalty incurred by the processor due to the mispredicted branch

Method and system for minimizing branch misprediction penalties within a processor

Comparator circuitry and a method of operation are provided. First and second match lines are precharged. First and second information are compared, and the first match line is selectively discharged in response thereto. Third and fourth information are compared, and the second match line is selectively discharged in response thereto. The second match line is discharged in response to discharging the first match line.

Comparator circuitry and method of operation

Performance modeling was used in conjunction with application code traces to tune the PowerPC 603 microprocessor design This modeling technique allowed the design space to be constrained by performance, power and size Trade-offs were examined with high confidence of final performance Sampled traces provided a fast turnaround for evaluation of the design space Finally, simulation model execution of fragments of the traces verified the performance model accuracy >

The PowerPC 603 microprocessor: performance analysis and design trade-offs

A processing system and method of operation are provided. First translation information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first translation information and a first portion of a first address. Second translation information is stored. A logic state of a second match line is selectively modified in response to a comparison between the second translation information and a second portion of the first address. The logic state of the second match line is selectively modified in response to the logic state of the first match line. A second address is selectively output in response to the logic state of the second match line.

Translation lookaside buffer for faster processing in response to availability of a first virtual address portion before a second virtual address portion

Carl D. Dietz

Papers

Content addressable memory circuitry and method of operation

Method and system for minimizing branch misprediction penalties within a processor

Comparator circuitry and method of operation

The PowerPC 603 microprocessor: performance analysis and design trade-offs

Translation lookaside buffer for faster processing in response to availability of a first virtual address portion before a second virtual address portion