Proceedings ArticleDOI
The PowerPC 603 microprocessor: performance analysis and design trade-offs
A. Poursepanj,D. Ogden,B. Burgess,S. Gary,Carl D. Dietz,D. Lee,S. Surya,M. Peters +7 more
- pp 316-323
TLDR
Performance modeling was used in conjunction with application code traces to tune the PowerPC 603 microprocessor design and simulation model execution of fragments of the traces verified the performance model accuracy.Abstract:
Performance modeling was used in conjunction with application code traces to tune the PowerPC 603 microprocessor design This modeling technique allowed the design space to be constrained by performance, power and size Trade-offs were examined with high confidence of final performance Sampled traces provided a fast turnaround for evaluation of the design space Finally, simulation model execution of fragments of the traces verified the performance model accuracy >read more
Citations
More filters
Proceedings ArticleDOI
Representative traces for processor models with infinite cache
TL;DR: The introduction of a new metric, called the R-metric, to evaluate the representativeness of reduced traces when applied to a wide class of processor designs and the development of a novel graph-based heuristic to generate reduced traces based on the notions incorporated in the metric.
Journal ArticleDOI
PowerPC 603, a microprocessor for portable computers
TL;DR: The PowerPC 603 incorporates a variety of features to reduce power dissipation: dynamic idle-time shutdown of separate execution units, low-power cache design, and power considerations for standard cells, data-path elements, and clocking.
Journal ArticleDOI
The PowerPC performance modeling methodology
TL;DR: The PowerPC performance modeling was based on trace-driven simulation, where the microprocessor organization is specified as a model, benchmark traces are generated and applied to the model, and performance data is measured and analyzed.
Proceedings ArticleDOI
The PowerPC 603 microprocessor: a low-power design for portable applications
TL;DR: Various design features optimize the PowerPC 603 for both power and performance, creating an ideal microprocessor solution for portable applications.
Proceedings ArticleDOI
The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor
Bradley G. Burgess,M. Alexander,Ying-Wai Ho,S.P. Litch,S. Mallick,D. Ogden,Sung-Ho Park,J. Slaton +7 more
TL;DR: The PowerPC 603 microprocessor is the second member of the PowerPC microprocessor family featuring low power operation of less than 3 watts while maintaining high performance of 75 SPECint92 (estimated) at 80 MHz.
References
More filters
Proceedings ArticleDOI
Branch prediction for free
Thomas Ball,James R. Larus +1 more
TL;DR: This work presents a program-based branch predictor that performs well for a large and diverse set of programs written in C and Fortran and focuses on heuristics for predicting non-loop branches, which dominate the dynamic branch count of many programs.
Proceedings ArticleDOI
Predicting conditional branch directions from previous runs of a program
TL;DR: It is suggested that even code with a complex flow of control, including systems utilities and language processors written in C, are dominated by branches which go in one way, and that this direction usually varies little when one changes the data used as the predictor and target.
Journal ArticleDOI
Accurate low-cost methods for performance evaluation of cache memory systems
TL;DR: New methods of simulation based on statistical techniques are proposed for decreasing the need for large trace measurements and for predicting true program behavior, and a new concept of primed cache is introduced to simulate large caches by the sampling-based method.
Proceedings ArticleDOI
The PowerPC 603 microprocessor: a high performance, low power, superscalar RISC microprocessor
Bradley G. Burgess,M. Alexander,Ying-Wai Ho,S.P. Litch,S. Mallick,D. Ogden,Sung-Ho Park,J. Slaton +7 more
TL;DR: The PowerPC 603 microprocessor is the second member of the PowerPC microprocessor family featuring low power operation of less than 3 watts while maintaining high performance of 75 SPECint92 (estimated) at 80 MHz.
Journal ArticleDOI
Cache sampling by sets
L. Liu,J.-K. Peir +1 more
TL;DR: An approach to workload sampling in which, instead of selection of memory references based on the time parameter, sample decisions are based on where the cache is accessed and the heuristics are focused on analysis for set-associative caches.