List of Figures. List of Tables. Preface. Foreword. 1. Basic Concepts. 2. Evolutionary Algorithm MOP Approaches. 3. MOEA Test Suites. 4. MOEA Testing and Analysis. 5. MOEA Theory and Issues. 3. MOEA Theoretical Issues. 6. Applications. 7. MOEA Parallelization. 8. Multi-Criteria Decision Making. 9. Special Topics. 10. Epilog. Appendix A: MOEA Classification and Technique Analysis. Appendix B: MOPs in the Literature. Appendix C: Ptrue & PFtrue for Selected Numeric MOPs. Appendix D: Ptrue & PFtrue for Side-Constrained MOPs. Appendix E: MOEA Software Availability. Appendix F: MOEA-Related Information. Index. References.

/pdf/evolutionary-algorithms-for-solving-multi-objective-problems-2txxk4mqci.pdf

Evolutionary algorithms for solving multi-objective problems

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today's industrial designs.

/pdf/vpr-a-new-packing-placement-and-routing-tool-for-fpga-43qgnt5y3n.pdf

VPR: A new packing, placement and routing tool for FPGA research

We propose a new approach to robot path planning that consists of building and searching a graph connecting the local minima of a potential function defined over the robot's configuration space. A planner based on this approach has been implemented. This planner is consider ably faster than previous path planners and solves prob lems for robots with many more degrees of freedom (DOFs). The power of the planner derives both from the "good" properties of the potential function and from the efficiency of the techniques used to escape the local min ima of this function. The most powerful of these tech niques is a Monte Carlo technique that escapes local min ima by executing Brownian motions. The overall approach is made possible by the systematic use of distributed rep resentations (bitmaps) for the robot's work space and configuration space. We have experimented with the plan ner using several computer-simulated robots, including rigid objects with 3 DOFs (in 2D work space) and 6 DOFs (in 3D work space) and ...

Robot motion planning: a distributed representation approach

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

TimberWolf is an integrated set of placement and routing optimization programs. The general combinatorial optimization technique known as simulated annealing is used by each program. Programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing, have been developed. Experimental results on industrial circuits show that area savings over existing layout programs ranging from 15 to 62% are possible.

/pdf/the-timberwolf-placement-and-routing-package-56cv7755ud.pdf

The TimberWolf placement and routing package

TimberWolf3.2 is a new standard cell placement and global routing package. The placement and global routing proceed over 3 distinct stages. The general combinatorial optimization technique known as simulated annealing is used during the first two stages of the placement. In the first stage, TimberWolf3.2 places the cells such that the total estimated interconnect cost is minimized. During the second stage, TimberWolf3.2 inserts feed through cells as required and the minimization of the total estimated interconnect cost proceeds again in the manner of simulated annealing. The second stage comes to a close following a global routing step, in which the number of wiring tracks needed is accurately estimated. During the third and final stage, local changes are made to the placement whenever such changes result in a reduction in the number of wiring tracks required. TimberWolf3.2 has achieved area savings ranging from 15 to 75% in experiments on numerous industrial circuits.

http://homepages.cae.wisc.edu/~ece556/spring2001/hw5/timberwolf.pdf

TimberWolf3.2: A New Standard Cell Placement and Global Routing Package

1 Introduction.- 1.1 Placement and Global Routing of Integrated Circuits.- 1.2.1 The gate array placement and global routing problem.- 1.2.2 The standard cell placement and global routing problem.- 1.2.3 The macro/custom cell placement and global routing problem.- 1.3 Previous Approaches to Placement and Global Routing.- 1.3.1 Previous placement methods.- 1.3.2 Previous global routing methods.- 1.4 A New Approach to Cell-Based Placement and Global Routing.- 2 The Simulated Annealing Algorithm.- 2.1 Introduction.- 2.2 The Basic Simulated Annealing Algorithm.- 2.3 Theoretical Investigations of the Simulated Annealing Algorithm.- 2.4 Overview of Work on General Annealing Schedules.- 2.4.1 The initial temperature.- 2.4.2 The temperature decrement.- 2.4.3 The equilibrium condition.- 2.4.4 The stopping, or convergence, criterion.- 2.5 Implementations of Simulated Annealing for Placement and Global Routing.- 2.6 The Function f().- 2.7 Fast Evaluation of the Exponential Function.- 3 Placement and Global Routing of Standard Cell Integrated Circuits.- 3.1 Introduction.- 3.2 The General TimberWolfSC Methodology.- 3.2.1 Finding the optimal target row lengths.- 3.2.2 Critical-net weighting.- 3.3 The Algorithm for Stage 1 of TimberWolfSC.- 3.3.1 The cost function.- 3.3.1.1 The first term in the cost function.- 3.3.1.2 The second term in the cost function.- 3.3.1.3 The third term in the cost function.- 3.3.2 An alternative objective function.- 3.3.3 The generation of new states function.- 3.3.4 The inner loop criterion.- 3.3.5 The range limiter.- 3.3.6 The control of T.- 3.3.7 The effects of net weighting.- 3.4 The Algorithms for Stage 2 of TimberWolfSC.- 3.4.1 Implementation of the stage 2 simulated annealing functions.- 3.4.2 The first phase of the global router.- 3.4.3 The second phase of the global router.- 3.5 The Algorithm for Stage 3 of TimberWolfSC.- 3.6 TimberWolfSC Results.- 3.6.1 Comparisons taken at the end of stage 1.- 3.6.2 The effectiveness of the global router.- 3.6.3 The effectiveness of stage 3 of TimberWolfSC.- 3.6.4 TimberWolfSC comparisons including stage 3.- 4 Macro/Custom Cell Chip-Planning, Placement, and Global Routing.- 4.1 Introduction.- 4.2 The General TimberWolfMC Methodology.- 4.2.1 Algorithms for handling rectilinear ceils.- 4.2.1.1 The bust() algorithm.- 4.2.1.2 The unbust() algorithm.- 4.2.2 Generating the initial placement configuration.- 4.2.3 Custom-cell pin placement.- 4.2.3.1 Introduction to the TimberWolfMC pin site methodology.- 4.3 The Algorithm for Stage 1 of TimberWolfMC.- 4.3.1 The cost function.- 4.3.1.1 The first term in the cost function.- 4.3.1.2 The second term in the cost function.- 4.3.1.3 The third term in the cost function.- 4.3.2 The generate() function.- 4.3.2.1 Introduction.- 4.3.2.2 The Range Limiter.- 4.3.2.3 Single-cell displacement-point selection.- 4.3.3 Additional stage 1 simulated annealing algorithmic details.- 4.4 The Algorithms for Stage 2 of TimberWolfMC.- 4.4.1 Channel generation.- 4.4.2 Global routing.- 4.4.3 Placement refinement.- 4.5 TimberWolfMC Results.- 4.6 Conclusion.- 5 Average Interconnection Length Estimation.- 5.1 Introduction.- 5.2 The Placement Model.- 5.3 Previous Approaches.- 5.4 Average Interconnection Length for Random Placements under the Assumption of Two-Pin Nets.- 5.4.1 Practical considerations.- 5.5 Average Interconnection Length for Random Placements Having Nets of Arbitrary Pin Counts.- 5.5.1 Results.- 5.6 A Model for Optimized Placement.- 5.6.1 The average number of other cells connected to a cell.- 5.6.1.1 The new method.- 5.6.1.2 Practical considerations.- 5.6.1.3 Results.- 5.6.2 A notion of optimized placement.- 5.6.3 The enclosing Cm x Cs rectangles.- 5.7 Results.- 6 Interconnect-Area Estimation for Macro Cell Placements.- 6.1 Introduction.- 6.2 Interconnect-Area Estimation Based on Average Net Traffic.- 6.3 Baseline Channel Width Modulation Based on Channel Position.- 6.4 Associating the Estimated Interconnect Area with the Cell Edges.- 6.5 Interconnect-Area Estimation as a Function of Relative Pin Density.- 6.6 The Implementation of the Dynamic Interconnect-Area Estimator.- 6.7 Results.- 7 An Edge-Based Channel Definition Algorithm for Rectilinear Cells.- 7.1 Introduction.- 7.2 The Basic Channel Definition Algorithm.- 7.2.1 Identifying critical cell-edge pairs.- 7.2.2 Characterization of fixed cell edges.- 7.2.3 An algorithm for finding critical regions.- 7.3 The Generation of the Channel Graph.- 7.4 The Generation of the Channel Routing Order.- 8 A Graph-Based Global Router Algorithm.- 8.1 Introduction.- 8.2 Basic Graph Algorithms Used by the Global Router.- 8.2.1 Prim's algorithm for the minimum spanning tree problem.- 8.2.2 Dijkstra's algorithm for the shortest path problem.- 8.2.3 Lawler's algorithm for finding the M-shortest paths.- 8.3 The Algorithm for Generating M-Shortest Routes for a Net.- 8.4 The Second Phase of the Global Router Algorithm.- 8.5 Results.- 9 Conclusion.- 9.1 Summary.- 9.2 Future Work.- 9.2.1 Simulated annealing.- 9.2.2 Row-based cell placement.- 9.2.3 Row-based global routing.- 9.2.4 Macro/custom cell placement.- 9.2.5 Interconnection length estimation.- 9.2.6 Channel definition.- 9.2.7 Graph-based global routing.- Appendix Island-Style Gate Array Placement.- A.1 Introduction.- A.2 The Implementation of the Simulated Annealing Functions.- A.2.1 The generation of new states.- A.2.2 The cost function.- A.2.2.1 The first cost function.- A.2.2.2 The second cost function.- A.2.3 The inner loop criterion.- A.2.5 The stopping criterion.- A.3 Results.- A.3.1 Performance comparison of the two cost functions.- A.3.2 Performance comparison on benchmark problems.

VLSI Placement and Global Routing Using Simulated Annealing

We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of the art. Our timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. A novel pinpair algorithm controls the delay without the need for user path specification. The timing algorithm is generally applicable to hierarchical, iterative placement methods. Using this algorithm, we present results for the only MCNC standard cell benchmark circuits (fract, struct, and avq.small) for which timing information is available. We decreased the delay of the longest path of circuit fract by 36% at an area cost of only 2.5%. For circuit struct, the delay of the longest path was decreased by 50% at an area cost of 6%. Finally, for the large (22,000 cell) circuit avq.small, the longest path delay was decreased by 28% at an area cost of 6% yet only doubling the execution time. This is the first report of timing driven placement results for any MCNC benchmark circuit.

/pdf/timing-driven-placement-for-large-standard-cell-circuits-3zzosvimr6.pdf

Timing Driven Placement for Large Standard Cell Circuits

We present two major extensions to the implementation of simulated annealing for row-based placement which have enabled it to obtain the best results ever reported for a large set of MCNC benchmark circuits while using the least computation time ever reported for remotely comparable results. Our results indicate that chip area reductions up to 16% can be expected, compared with TimberWolfSC v6.0. Our new hierarchical annealing-based placement program yields total wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. In comparison to the Gordian/Domino program, our new program yields total wire lengths which are always lower (up to 9% lower) and our program is always faster for circuits with more than 5000 cells (which represents the range of circuit sizes of interest).

Carl Sechen

Papers

The TimberWolf placement and routing package

TimberWolf3.2: A New Standard Cell Placement and Global Routing Package

VLSI Placement and Global Routing Using Simulated Annealing

Timing Driven Placement for Large Standard Cell Circuits

Efficient and effective placement for very large circuits