Showing papers by "Chadi Jabbour published in 2009"

A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΣΔ ADC

Abstract: This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΣΔ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΣΔ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm2.

A 65 nm CMOS versatile ADC using time interleaving and ΣΔ modulation for multi-mode receiver

Abstract: High performances wideband Analog to Digital Converter (ADC) remains a bottleneck to realize software and cognitive radio receivers. Time Interleaved Sigma-Delta (TIΣΔ) architecture is a good candidate to increase the bandwidth of the data converters with the lowest hardware complexity compared to other solutions using parallel sigma-delta modulators. This paper proposes a reconfigurable 4 channels TIΣΔ using the novel GMSCL (General Multi Stage Closed Loop) sigma-delta architecture and a new digital processing reducing considerably the hardware complexity. The sigma-delta modulators have been designed using switched-capacitor technique and implemented with STMicroelectronis 65 nm CMOS technology. Three different scenarios are possible : the first one for GSM standard clocked at 26 MHz and consumes 2.59 mW, the second one for UMTS/DVB-T standards clocked at 208 MHz and consumes 46 mW and the last one for WiFi/WiMax standards clocked at 208 MHz and consumes 92 mW. The total circuit die area is equal to 3 mm2. The digital filtering was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. For a clock rate of 208 MHz, the evaluated die area is 0.115 mm2.

A 65nm CMOS EDGE/UMTS/WLAN tri-mode four-channel time-interleaved ΣΔ ADC

Abstract: A four-channel time-interleaved ΣΔ analog-to-digital-converter for EDGE/UMTS/WLAN tri-mode zero-IF receiver is presented. The number of time-interleaved channels, the clock rate and the order of the modulators are programmable. The former adapts the conversion bandwidth to the selected standard while the two last are set to reach dynamic range specifications. Each channel uses a Global Multi-Stage Closed-Loop ΣΔ modulator which is a novel cascade 2-2 topology. A Sample-And-Hold circuit is used at the front-end of the ADC to reduce the clock skew issue inherent to time-interleaved converters. The prototype chip was implemented in a 1.2V 65nm CMOS process using metal-insulator-metal capacitors. Simulated dynamic range is 80dB/80dB/50dB in 135KHz/2MHz/12.5MHz respectively. The number of active channels in EDGE/UMTS/WLAN mode is one, two and four respectively which leads to a power consumption of 3.1mW/55.2mW/110.4mW. Clocked at 208MHz, the analog front-end exhibits an SFDR less than −90dB over 2MHz bandwidth and consumes 12mW. The total active die area is 2.2mm².