IEEE International Solid-State Circuits Conference

This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.

A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

We consider minimal-rate sampling schemes for infinite streams of delayed and weighted versions of a known pulse shape. The minimal sampling rate for these parametric signals is referred to as the rate of innovation and is equal to the number of degrees of freedom per unit time. Although sampling of infinite pulse streams was treated in previous works, either the rate of innovation was not achieved, or the pulse shape was limited to Diracs. In this paper we propose a multichannel architecture for sampling pulse streams with arbitrary shape, operating at the rate of innovation. Our approach is based on modulating the input signal with a set of properly chosen waveforms, followed by a bank of integrators. This architecture is motivated by recent work on sub-Nyquist sampling of multiband signals. We show that the pulse stream can be recovered from the proposed minimal-rate samples using standard tools taken from spectral estimation in a stable way even at high rates of innovation. In addition, we address practical implementation issues, such as reduction of hardware complexity and immunity to failure in the sampling channels. The resulting scheme is flexible and exhibits better noise robustness than previous approaches.

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Multichannel Sampling of Pulse Streams at the Rate of Innovation

Nowadays, a large amount of information has to be transmitted or processed. This implies high-power processing, large memory density, and increased energy consumption. In several applications, such as imaging, radar, speech recognition, and data acquisition, the signals involved can be considered sparse or compressive in some domain. The compressive sensing theory could be a proper candidate to deal with these constraints. It can be used to recover sparse or compressive signals with fewer measurements than the traditional methods. Two problems must be addressed by compressive sensing theory: design of the measurement matrix and development of an efficient sparse recovery algorithm. These algorithms are usually classified into three categories: convex relaxation, non-convex optimization techniques, and greedy algorithms. This paper intends to supply a comprehensive study and a state-of-the-art review of these algorithms to researchers who wish to develop and use them. Moreover, a wide range of compressive sensing theory applications is summarized and some open research challenges are presented.

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A Review of Sparse Recovery Algorithms

This paper details the Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. It is shown the practical suitability of PSO to solve both mono-objective and multiobjective discrete optimization problems. Two application examples are presented: maximizing the voltage gain of a low noise amplifier for the UMTS standard and computing the Pareto front of a bi-objective problem, maximizing the high current cut off frequency and minimizing the parasitic input resistance of a second generation current conveyor. The aptness of PSO to optimize difficult circuit problems, in terms of numbers of parameters and constraints, is shown.

Analog circuit design optimization through the particle swarm optimization technique

In this paper, we propose an improved translinear based CCII configuration. Heuristic algorithm is used for optimal sizing regarding static and dynamic performances. PSPICE simulations for AMS 0.35 ?m CMOS technology show that the current and voltage bandwidths are respectively 2.6 GHz and 3.9 GHz, and the parasitic resistance at port X (RX) has a value of 18 ? for a control current of 100 ?A. The improved configuration is used as a building block into high frequency design applications: a current controlled oscillator and a tunable fully integrable band pass filter. The oscillator frequency can be tuned in the range of [290---475 MHz] by a simple variation of a DC current. The central frequency of the band pass filter can be varied in the range of [1.22---1.56 GHz] and the quality factor vary in the range [8---306] with a simple variation of a DC current.

A high performances CMOS CCII and high frequency applications

Clock-skew errors in time-interleaved (TI) analog-to-digital converters (ADCs) importantly degrade the linearity of such converters. These nearly constant but unknown errors, which must not be confused with random jitter, prevent TI ADCs from performing uniform sampling. This paper proposes a mixed-signal clock-skew calibration technique and explores its limitations to perform a background calibration. Compared to the existing all-digital calibration techniques, ours distinguishes itself by the simplicity of its hardware elements. On the other hand, compared to the all-analog ones, ours keeps the inherent robustness of a digital clock-skew detection. A demonstrator shows the feasibility of our technique. This demonstrator consists of two 10-bit commercial ADCs, a field-programmable gate array to implement a digital clock-skew detector, and an application-specific integrated circuit in a CMOS 0.35-mum technology to implement a digitally trimmable multiphase sampling clock generator. In this highly hostile environment of interconnected discrete components, our demonstrator can correct an initial clock skew of thousands of picoseconds with a granularity of 1.8 ps.

Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs

A four-quadrant class AB CMOS current-multiplier is presented. Wide input range, high dynamic range, high cutoff frequency, good linearity and low consumption are the features of the presented technique. A nonlinearity error of 1.1 % with a small-signal bandwidth of 66 MHz for a quiescent current of 25 µA and a supply voltage of 3.3 V in a 0.5 µm technology are obtained.

Four-quadrant class AB CMOS current multiplier

A reconfigurable RF sampling receiver for multistandard applications

A novel output stage for OTAs and opamps for gain enhancement is described. The proposed circuit using positive feedback to cancel the output conductance allows the DC gain to be enhanced without affecting the bandwidth of the OTA and opamp.

Patrick Loumeau

Papers

A high performances CMOS CCII and high frequency applications

Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs

Four-quadrant class AB CMOS current multiplier

A reconfigurable RF sampling receiver for multistandard applications

Novel output stage for DC gain enhancement of opamp and OTA