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Showing papers by "Chandra Mouli published in 2021"


Patent
18 Feb 2021
TL;DR: In this article, the authors present an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor, and a two-dimensional material between a portion of the semiconducting material and the metal containing material.
Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less- doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source/drain region.

Patent
12 Jan 2021
TL;DR: In this article, the authors proposed a channel conduction in a semiconductor device, where a gate opposing the channel is added to the active area of the device to counter the channel bias.
Abstract: The invention relates to channel conduction in a semiconductor device. An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to thefirst source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.