C
Chang-seung Lee
Researcher at Samsung
Publications - 87
Citations - 1084
Chang-seung Lee is an academic researcher from Samsung. The author has contributed to research in topics: Layer (electronics) & Substrate (printing). The author has an hindex of 16, co-authored 87 publications receiving 1054 citations.
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Patent
Transistors and methods of manufacturing the same
TL;DR: In this article, the authors defined a patterned graphene region, defined by a region converted from graphene, and a gate of the transistor may include graphene, which is defined as a region of interest.
Patent
Monolithic ink-jet printhead and method for manufacturing the same
TL;DR: In this article, an ink-jet printhead and a method of manufacturing the same include a substrate on which a heater and a passivation layer protecting the heater are formed, a passage plate on which an ink chamber corresponding to the heater and an ink passage connected to the ink chamber are formed.
Patent
Bubble-jet type ink-jet printhead and manufacturing method thereof
TL;DR: In this paper, a bubble-jet type ink-jet printhead is presented, which includes a substrate integrally having an ink supply manifold, an ink chamber and an ink channel, a nozzle plate having a nozzle, a heater consisting of resistive heating elements, and an electrode for applying current to the heater.
Journal ArticleDOI
Clean transfer of graphene and its effect on contact resistance
Jooho Lee,Jooho Lee,Yongsung Kim,Hyeon-Jin Shin,Chang-seung Lee,Dongwook Lee,Chang Yul Moon,Juhwan Lim,Seong Chan Jun +8 more
TL;DR: In this article, a gold-assisted transfer method producing no polymer residue on the graphene surface is introduced, and then the gold film is used directly as an electrode to form the transfer length pattern for calculating the contact resistance.
Proceedings ArticleDOI
MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes
TL;DR: In this paper, self-aligned TaN and TaN/poly-Si gated n-MOSFETs with ultra thin (EOT=11 /spl Aring/) CVD ZrO/sub 2/ gate dielectrics were successfully fabricated and characterized.