The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor (MOS) gate stacks was explored. Metal work functions on high-κ dielectrics are observed to differ appreciably from their values on SiO2 or in vacuum. We applied the interface dipole theory to the interface between the gate and the gate dielectric of a MOS transistor and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for gate dielectrics like SiO2, Al2O3, Si3N4, ZrO2, and HfO2 were extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate work functions on the gate dielectric material. Challenges for gate work function engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future MOS technology incorporating high-κ gate dielectrics.

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Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.

High-/spl kappa//metal-gate stack and its MOSFET characteristics

A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the subsequent converting step includes oxidizing a metal atomic layer to form a metal oxide layer. The atomic layer deposition and oxidation step are then repeated to produce a metal oxide layer having sufficient thickness for use as a metal oxide layer in an integrated circuit. The subsequent converting step, in an embodiment, includes converting the atomic deposition layer by exposing it to one of nitrogen to form a nitride layer, carbon to form a carbide layer, boron to form a boride layer, and fluorine to form a fluoride layer. Systems and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method are also described.

Atomic layer deposition and conversion

A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF 5 and NH 3 . In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.

Enhanced atomic layer deposition

A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode. Furthermore, the barrier film prevents the electrode material from reacting with the gate dielectric material. The barrier layer is ultra thin and, at the same time, it forms a uniform cover over the entire surface of the gate dielectric.

Method of depositing barrier layer from metal gates

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.

Dual-metal gate technology for deep-submicron CMOS transistors

In this paper, we have successfully fabricated and characterized self-aligned TaN and TaN/poly-Si gated n-MOSFETs with ultra thin (EOT=11 /spl Aring/) CVD ZrO/sub 2/ gate dielectrics. It is show that while both gate stacks show excellent leakage current and good thermal stability after a 900/spl deg/C, 30 s, N/sub 2/ anneal, the TaN/poly-Si ZrO/sub 2/ devices exhibit superior thermal stability even after 1000/spl deg/C, 30 s, N/sub 2/ anneal. In addition, the TaN/poly-Si devices show negligible frequency dependence of CV, charge trapping, and superior TDDB characteristics, compared to TaN devices. Well-behaved N-MOSFETs with both TaN and TaN/poly-Si gate electrodes are demonstrated.

https://www.vlsisymposium.org/Past/01web/technology/tec_pdf/T11p4.pdf

MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes

Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N 2 O oxidation of NH 3 -nitrided Si

P-MOSFETs with 14 /spl Aring/ equivalent oxide thickness (EOT) were fabricated using both JVD Si/sub 3/N/sub 4/ and RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO/sub 2/ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large.

H.F. Luan

Papers

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Dual-metal gate technology for deep-submicron CMOS transistors

MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes

Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N 2 O oxidation of NH 3 -nitrided Si

Two silicon nitride technologies for post-SiO 2 MOSFET gate dielectric