In recent years, the 2.5D IC (Integrated Circuit) package with TSV (Through Silicon Vias) has become important for high-bandwidth and high-performance applications. It is well known that 2.5D technology requires significant innovation in the areas of process technology, packaging, design, thermals, and test solutions leading to several hundred new technologies in a single product. With these complex material sets and process steps combined with new design requirements, methods, and components, a significant amount of research and engineering development is required to bring a successful product to market. After an 8 year development, in July of 2015 AMD reported it began shipment of a new generation of AMD Radeon Fury graphics cards, based on the development of the "Fiji" GPU and the first generation of High Bandwidth Memory (HBM1). This announcement is the next major step in an era for 2.5D IC package technology which will be used in a wide variety of applications. Given the scope of this undertaking many collaborations were required. This paper provides an overview of the collaboration between AMD and ASE. It chronicles the work from initial proof of concept to technology feasibility to product development to production ramp and ultimately high volume production. Details of several functional prototypes are outlined including warpage characterization, stress reduction, materials selection methodologies, and the use of finite element analysis (FEA) and advanced Warpage Metrology Analyzer (WMA) for optimization. The result is a reliable 2.5D process flow with >99% assembly yield for a 1011mm2 interposer with 5 dies attached in a 300+W 55x55mm2 package.

An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.

Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process ...

Development of Organic Multi Chip Package for High Performance Application

https://ir.nctu.edu.tw:443/bitstream/11536/21288/1/000314258600003.pdf

Reliability of key technologies in 3D integration

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the packa ...

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Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC packaging solution. As the 2.5D interposer design pushing towards smaller & shorter via due to I/O density and electrical performance, the warpage of thinner interposer is therefore much more challenging in thin wafer handling and assembly process. In this presentation, a TSV structure is introduced with fabricated interposer prototype, and could be assembled together with single-die/multi-chip on a substrate. The demonstrated interposer assembled in FCBGA (Flip Chip Ball Grid Array) has covered features such as low temperature fabrication process, low warpage, and low leakage with minimized TSV parasitic parameters. Electrical and stress characterizations, current density characterization up to 1100mA and Shadow Moire are performed and compared with simulation models for correlation study. Known-Good TSV and Si interposer are also reviewed and discussed in this presentation. Full validated reliability test, both die and package level, in conjunction with board level drop test, are presented to verify interposer fabrication, assembly process optimization, and interconnection stability.

TSV technology for 2.5D IC solution

In this study, measurements are made to validate the electrical performance of a Through Silicon Via (TSV) interconnection up to 40GHz, and the results of the wideband scalable model of TSV is proposed and compared with the measured data. Measurement of the TSV structure demonstrates its advantages of low parasitic capacitance and low insertion loss at high frequency.

Scalable modeling of Through Silicon Vias up to milimeter-wave frequency

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process. From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application. Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this ...

Chang-Ying Hung

Papers

TSV technology for 2.5D IC solution

Scalable modeling of Through Silicon Vias up to milimeter-wave frequency

GHz High Frequency TSV for 2.5D IC Packaging