A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.

Integrated circuit resistive devices including multiple interconnected resistance layers

The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.

Bonding pad and method of making same

Disclosed are a multi-layer substrate and a manufacture method thereof The multi-layer substrate of the present invention comprises a surface dielectric layer and at least one bond pad layer The surface dielectric layer is located at a surface of the multi-layer substrate The bond pad layer is embedded in the surface dielectric layer to construct the multi-layer substrate with the surface dielectric layer of the present invention The manufacture method of the present invention forms at least one bond pad layer on a flat surface of a carrier and then forms the surface dielectric layer to cover the bond pad layer where the bond pad layer is embedded therein After the multi-layer substrate is separated from the carrier, the bond pad layer and the surface dielectric layer construct a flat surface of the multi-layer substrate

Multi-layer substrate and manufacture method thereof

The present disclosure provides a method of manufacturing a semiconductor device The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure

Method of manufacturing semiconductor device

A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.

Method of making bond pad

A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 μm 2 and a PVD aluminum base conductor filled in the opening.

Alluminum base conductor for via fill interconnect

A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 mum and a PVD aluminum base conductor filled in the opening.

Method for producing semiconductor component and its semiconductor component

An aluminum base conductor for via fill interconnect and a semiconductor formed by the aluminum base conductor are provided, wherein the semiconductor includes a dielectric layer having a opening formed therein with a cross-sectional area of less than 1 μm2. The PVD aluminum base conductor is filled in the opening.

Chao-Hsiung Wang

Papers

Alluminum base conductor for via fill interconnect

Method for producing semiconductor component and its semiconductor component

Aluminum base conductor for via fill interconnect and applications thereof

Aluminum based conductor for via fill and interconnect