다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

About the Author.Foreword.Preface.Glossary.1. Introduction.2. Video Formats and Quality.3. Video Coding Concepts.4. The MPEG-4 and H.264 Standards.5. MPEG-4 Visual.6. H.264/MPEG-4 Part 10.7. Design and Performance.8. Applications and Directions.Bibliography.Index.

H.264 and MPEG-4 Video Compression: Video Coding for Next-generation Multimedia

We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.

https://www.pagiamtzis.com/pubs/pagiamtzis-jssc2006.pdf

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey

Advances in wireless communication technologies, such as wearable and implantable biosensors, along with recent developments in the embedded computing area are enabling the design, development, and implementation of body area networks. This class of networks is paving the way for the deployment of innovative healthcare monitoring applications. In the past few years, much of the research in the area of body area networks has focused on issues related to wireless sensor designs, sensor miniaturization, low-power sensor circuitry, signal processing, and communications protocols. In this paper, we present an overview of body area networks, and a discussion of BAN communications types and their related issues. We provide a detailed investigation of sensor devices, physical layer, data link layer, and radio technology aspects of BAN research. We also present a taxonomy of BAN projects that have been introduced/proposed to date. Finally, we highlight some of the design challenges and open issues that still need to be addressed to make BANs truly ubiquitous for a wide range of applications.

Body Area Networks: A Survey

This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syn- drome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After imple- mented with 0.18- m 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm silicon area, and the average core power consumption is 68.1 mW. Index Terms—Error-and-erasure correction, Montgomery mul- tiplication, Reed-Solomon (RS) code, universal architecture.

/pdf/a-universal-vlsi-architecture-for-reed-solomon-28tgdbk0a3.pdf

A Universal VLSI Architecture for Reed-Solomon

We propose a novel bit plane error resilient entropy coding scheme for DCT-based image compression, which can control and minimize the error propagation effect. The compressed rate is similar to the JPEG standard. However, it uses only 18 VLC symbols. Hardware implementation cost and power consumption can then be minimized. Base on simulation results, the proposed coding scheme can achieve high image quality (PSNR=29.82 dB) even at bit error rate of 10/sup -3/. An image codec has been implemented for verifying the proposed bit-plane EREC coding technique. It can compress and decompress CIF size (352/spl times/288, 4:2:0 format) images at the rate of 30 frames per second using 20 MHz clock rate. It only occupies 36 k gate count and 1.90/spl times/1.90 mm/sup 2/ silicon area in a 0.35 /spl mu/m CMOS process. With 3.3 V power supply, the simulated power consumption is only 27 mWatt and 0.41 mA/MHz. This performance can meet various wireless portable multimedia system requirements.

A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication

For PHM(Predictive Health Management) in an industrial scenario, motor vibration anomaly detection requires a large number of labeled data. The problem is that the anomaly vibration signal data is scarce and difficult to be obtained, especially the problem of insufficient data in the building and deployment of multi-machine models. This paper proposes a Meta-learning method based on deep unsupervised learning(Autoencoder). We use non-labeled and a small amount of vibration signal data which is converted into 52 key physical and statistical features to build models of different motors. By inputting these 52 features into designed models, other 52 features can be reconstructed as output. We use input and output features to calculate reconstruction error which is used as the criterion for the performance of models. We also use accuracy as the criterion for the performance of models. In the actual industrial situation, the improvement of accuracy by our proposed method is about 33.50% better than the method only with unsupervised learning for the new sensor model with few vibration data.

Fast Adaption for Multi Motor Anomaly Detection via Meta Learning and deep unsupervised learning

This paper presents the results of the first ASIC implementation of the authenticated encryption scheme KetjeSR. The design covers the encryption and decryption operation in combination with a handshake protocol for the data transfer. The chip implementation was done in a TSMC 90nm GUTM process. The encryption/decryption module has an area footprint of 12.2kGE. The processor reaches an end-to-end throughput of 2.08 Gbps when running at a clock frequency of 130 MHz. The design was further optimized for low power and consumes 2.421 mW. The optimization is based on the reuse of the permutation function in combination with extensive pipelining. In terms of energy, the encryption operation costs 1.16 pJ/bit.

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR

With the rapid advance in CMOS technology, the trend of the VLSI then towards system-on-chip (SOC) where design methodology, cost, and turnaround time are major issues. Concepts of intellectual property (IP) are then proposed to fit for SOC designs. Based on a DFS controller IP, a wideband digital frequency synthesizer (DFS) is proposed to fit in with the wireless LAN applications, which provides low cost and efficient design periods. A 2-stage voltage-controlled oscillator (VCO) is designed to achieve the system requirements and generates such a high-speed frequency. Its output frequency range can be from 465 MHz to 2.635 GHz with double 3.0-V supplies. Besides, a novel cell-based digital-to-voltage converter (DVC) is also proposed to solve the interface between the DFS controller IP and the VCO. The wideband DFS is fabricated in 0.35-um SPQM CMOS technology.

/pdf/a-wideband-digital-frequency-synthesizer-40bgiw6sih.pdf

Chen-Yi Lee

Papers

A Universal VLSI Architecture for Reed-Solomon

A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication

Fast Adaption for Multi Motor Anomaly Detection via Meta Learning and deep unsupervised learning

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR

A wideband digital frequency synthesizer