다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

About the Author.Foreword.Preface.Glossary.1. Introduction.2. Video Formats and Quality.3. Video Coding Concepts.4. The MPEG-4 and H.264 Standards.5. MPEG-4 Visual.6. H.264/MPEG-4 Part 10.7. Design and Performance.8. Applications and Directions.Bibliography.Index.

H.264 and MPEG-4 Video Compression: Video Coding for Next-generation Multimedia

We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.

https://www.pagiamtzis.com/pubs/pagiamtzis-jssc2006.pdf

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey

Advances in wireless communication technologies, such as wearable and implantable biosensors, along with recent developments in the embedded computing area are enabling the design, development, and implementation of body area networks. This class of networks is paving the way for the deployment of innovative healthcare monitoring applications. In the past few years, much of the research in the area of body area networks has focused on issues related to wireless sensor designs, sensor miniaturization, low-power sensor circuitry, signal processing, and communications protocols. In this paper, we present an overview of body area networks, and a discussion of BAN communications types and their related issues. We provide a detailed investigation of sensor devices, physical layer, data link layer, and radio technology aspects of BAN research. We also present a taxonomy of BAN projects that have been introduced/proposed to date. Finally, we highlight some of the design challenges and open issues that still need to be addressed to make BANs truly ubiquitous for a wide range of applications.

Body Area Networks: A Survey

This paper presents an extrinsic data compression method for double-binary turbo codes. Frame and extrinsic data memory occupy more area in turbo decoder implementations with the frame size increasing. Besides, non-binary turbo codes have much more extrinsic memory usage than single-binary turbo codes. This proposed compression method utilizes an operation in radix-4 single-binary turbo decoder and also can simplify the integration of single and double-binary turbo decoders in hardware implementations. It can reduce one-third of extrinsic memory size, about 15% of total memory usage. Simulation results show that this method only causes 0.2dB performance loss when bit error rate is equal to 10−5 with slight hardware increment.

Extrinsic data compression method for double-binary turbo codes

A 180 nm phase-change device is developed for embedded SoC memory to replace both DRAM and Flash memories. In order to reduce power consumption, the total volume of the device must be reduced and the programming speed must be increased. The speed of programming and reading of chalcogenide memory devices is investigated. It is discovered that the writing speed of the devices using Ge/sub 2/Sb/sub 2/Te/sub 5/ as the storage media is compromised when the chalcogenide film is ultra thin. With doping of Sn, the writing speed is dramatically increased. The maximum programming time (SET) is reduced from 200 ns to 40 ns and that for RESET from 40 ns to 10 ns. Moreover, the reading speed is also improved as a result of lower resistance.

180nm Sn-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ chalcogenide phase-change memory device for low power, high speed embedded memory for SoC applications

A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted in our FFT processor A test chip for 8 K mode DVB-T system has been designed and fabricated using 018 /spl mu/m CMOS process with core area of 484 mm/sup 2/ and consumes only 252 mW at 20 MHz

A new dynamic scaling FFT processor

In this paper, a high-performance and low-cost COFDM baseband processor is presented. With algorithm exploration in channel estimation and phase error tracking, synchronization becomes more robust to enhance system performance. And better design SNR (1.35/spl sim/7.16dB) can be achieved compared to current solutions. Moreover through architectural exploration, the proposed baseband processor designed in 0.18um CMOS process contains only 370K logic gates and 3.3Kbyte memory. Measurement results show that better hardware efficiency and performance enhancement is achieved for high-speed WLAN applications.

/pdf/a-cofdm-baseband-processor-with-robust-synchronization-for-4p2yzd7653.pdf

A COFDM baseband processor with robust synchronization for high-speed WLAN applications

A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal.

https://ir.nctu.edu.tw:443/bitstream/11536/105423/1/20100090769.pdf

Chen-Yi Lee

Papers

Extrinsic data compression method for double-binary turbo codes

180nm Sn-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ chalcogenide phase-change memory device for low power, high speed embedded memory for SoC applications

A new dynamic scaling FFT processor

A COFDM baseband processor with robust synchronization for high-speed WLAN applications

Digital loop filter for all-digital phase-locked loop design