Chiao-Wei Tseng

TL;DR: In this paper, a novel strategy to increase the strain of a lead-free ferroelectric system via material structure design to create polar nano regions (PNRs) and point defects in the material while retaining the global phase was introduced.

TL;DR: High-performance field-effect transistors based on the Au-NPs-embedded pentacene films can be prepared if the nanoparticles are made "hydrophobic" as well as "oleophobic" by appropriate SAMs.

TL;DR: The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time, while with clusters of azo moieties as the trap sites, the switching is faster but the retention is shorter.

TL;DR: Gold nanoparticles with surfaces covered with a self-assembled monolayer of azobenzene derivatives were prepared at the interface of dielectric insulator SiO2 and pentacene thin film and resulted in a transistor memory device with about 70% more charges trapped, much faster response time as well as higher retention time.

TL;DR: A flexible, low-voltage, and nonvolatile memory device was fabricated by implanting a functional monolayer on an aluminum oxide dielectric surface in a pentacene-based organic transistor that exhibited rather stable device characteristics upon bending of the polymeric substrate.