High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multi-media to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit micro-controller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter.

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Technologies for Ultradynamic Voltage Scaling

The demand of high quality video and high data compression enables MPEG-4 AVC/H.264 to adopt the context-based adaptive variable length code (CAVLC) technique contrary to the traditional MPEG-4 VLC techniques. The paper presents a novel, low-cost, high-performance VLSI architecture design for MPEG-4 AVC/H.264 CAVLC decoding. We exploit five different techniques to reduce both the hardware cost and power consumption, and to increase the data throughput rate. They are PCCF (partial combinational component freezing), HLLT (hierarchical logic for look-up tables), ZTEBA (zero-left table elimination by arithmetic), IDS (interleaved double stacks), and ZCS (zero codeword skip). The proposed design can decode every syntax element per cycle. The synthesis result shows that the design achieves maximum speed at 175 MHz. When we synthesize the proposed design at the clock constraint of 125 MHz, the hardware cost is about 4720 gates under a 0.18 /spl mu/m CMOS technology, which achieves the real-time processing requirement for H.264 video decoding on HD1080i format video.

A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096×2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

A multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder includes 252kgates and 4.9kB internal memory in a core size of 4.2times1.2mm 2 using 0.13mum 1P8M CMOS. The power consumption at 1.2V supply is 71 mW at 120MHz for real-time HD1080 and 7.9mW at 20MHz for real-time H.264 decoding of D1 video

A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications

This paper presents a high performance VLSI architecture design for MPEG-4 AVC/H264 CAVLC encoding In the proposed design, we propose a forward-based parallel coding (FPC) technique to increase the data throughput rate Moreover, two approaches called arithmetic table elimination (ATE) and fast look-up table matching (FLM) are exploited to reduce the hardware cost With the synthesis constraint of 125 MHz clock, the hardware cost of the proposed design is 9724 gates based on a 018/spl mu/m CMOS technology, which achieves the real-time processing requiremenwat for H264 video encoding on HD1080 format video

A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications

This paper proposes an area-efficient variable length decoder (VLD) IP core design for MPEG-1/2/4 video coding applications. The proposed IP core exploits the parallel numerical matching in the MPEG-1/2/4 entropy decoding to achieve high data throughput rate in terms of limited hardware cost. This feature not only improves the performance of VLD, but also facilitates reducing the power consumption through lowering down the supply voltage while maintaining enough data throughput rate. Moreover, we propose a partial combinational component enabling approach for minimizing the power consumption of the proposed design. Based on 0.18-mum CMOS technology, the implementation results show that the proposed IP core operates at 125-MHz clock frequency with the cost of 13 105 gates. In addition, the power consumption of the proposed design reaches 163.4 muW operated at 12.5 MHz with 0.9-V supply voltage, which is fast enough for MPEG-1/2/4 real-time decoding on 4CIF video@30 Hz. Compared to the existing designs, the proposed IP core possesses both higher data throughput and less hardware cost

An Area-Efficient Variable Length Decoder IP Core Design for MPEG- $hbox 1/2/4$ Video Coding Applications

The dynamic memory controller plays an important role in system-on-a-chip (SoC) designs to provide enough memory bandwidth through external memory for DSP and multimedia processing. However, the overhead cycles in accessing the data located in external memory have much influence on the SoC performance. In this paper, we propose a low latency memory controller with AHB interface to reduce the overhead cycles for the SDR memory access in the SoC designs. Through the pre-calculated addresses of impending transfers, two memory control schemes, i.e. Burst terminates Burst (BTB) and Anticipative Row Activation (ARA), are used to reduce the latency of SDR memory access. The experimental results show that the proposed memory controller reduces the memory bandwidth by 33% in a typical MPEG-4 video decoding system.

A Low Latency Memory Controller for Video Coding Systems

This article proposes a low-cost, low-power multistandard video decoder for high definition (HD) video applications. The proposed design supports multiple-standard (JPEG baseline, MPEG-1/2/4 Simple Profile (SP), and H.264 Baseline Profile (BP)) video decoding through interactive parsing control and common parameter bus interface. In order to reduce hardware cost, the shared adder-based structure and reusable data management are proposed to achieve hardware sharing and reduce internal memory size, respectively. In addition, the proposed design is optimized through reducing memory bandwidth by increasing both data reuse amount and burst length of memory access as well as eliminating cycle overhead in data access for supporting HD video decoding with single AHB-based SDR memory. The proposed 252Kgates/4.9kB/71mW/0.13μm multi-standard video decoder reduces 72p in gate count and 87p in power consumption as compared to the state-of-the-art design, when operating at 120MHz for real-time HD1080 video decoding with single AHB-based SDR memory.

Chih-Da Chien

Papers

A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications

A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications

An Area-Efficient Variable Length Decoder IP Core Design for MPEG- $hbox 1/2/4$ Video Coding Applications

A Low Latency Memory Controller for Video Coding Systems

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications